"Cadence has to get a new CEO who comes from within EDA; someone who
   knows what works and what's BS in EDA.  Otherwise, Cadence is screwed
   if they try to pawn off yet another non-EDA poser here.  There are too
   many big decisions right now that have to be made just right.  You need
   an EDA veteran for that; not a clueless pretty boy from a Big Name
   company that Wall Street likes.  A CEO needing EDA OJT won't cut it."

                                               - John Cooley
                                                 DeepChip.com

( ESNUG 476 Subjects ) ------------------------------------------ [10/29/08]

 Item  1: ( ESNUG 475 #5 ) Boatload of users talk up Mentor Sierra MCMM P&R
 Item  2: Strange equivalance problem with DW02_tree function in Formality
 Item  3: The top 20 best selling Springer/Kluwer books from DAC 2008
 Item  4: ( ESNUG 475 #6 ) Magma Titan (Sabio) analog migration ain't 1 day
 Item  5: ( ESNUG 472 #8 ) We use an EVE ZeBu-XXL 8 along with Bluespec BSV
 Item  6: ( ESNUG 475 #8 ) How Apache slowly crushes Cadence VoltageStorm
 Item  7: ( ESNUG 475 #9 ) IC Manage only one to pass this user ambush test
 Item  8: ( ESNUG 470 #1 ) Mentor TestKompress and EDT kicks ass in China
 Item  9: George is wrong; SystemC/C/C++ tools play nicely with each other
 Item 10: Packing guy asks on going from wirebond to flip chip and EDA tools

( ESNUG 476 White Papers ) -------------------------------------- [10/29/08]

    WP 1: Cliff Cummings & Real Intent's Clock Domain Crossing paper
    WP 2: IC Manage's IC Design Management Best Practices Paper

    These white papers at http://www.deepchip.com/whitepapers.html


============================================================================
 Trying to figure out a Synopsys bug?  Want to hear how 24,298 other users
    dealt with it?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
     !!!     "It's not a BUG,               
    /o o\  /  it's a FEATURE!"                 (508) 429-4357
   (  >  )
    \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
    _] [_         Verilog, VHDL and numerous Design Methodologies.

    Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
  Legal Disclaimer: "As always, anything said here is only opinion."
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   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)