Editor's Note: If you're an EDA VENDOR and you want your stuff to be
considered for My Cheesy Must See List for DAC, see:
http://www.deepchip.com/wiretap/080529.html
The DEADLINE is 4:00 Monday, June 2nd! Don't screw around! - John
( ESNUG 473 Subjects ) ------------------------------------------ [05/29/08]
Item 1: ( ESNUG 470 #1 ) We taped out 3 chips, all blocks done in Atoptech
Item 2: The new make_ccs_noise let us dump CeltIC for a pure PT-SI flow
Item 3: How is the industry going regarding System Verilog vs. Specman e?
Item 4: One analog designer's first look at the Ciranova Virtuoso killer
Item 5: ( ESNUG 472 #7 ) We don't use Cadence ETS; we use TimeCraft
Item 6: ( DVcon 07 #6 ) Understanding what the NuSym DeNibulator tool does
Item 7: ( ESNUG 469 #6 ) A 2nd look at Dafca ClearBlue silicon debug IP
Item 8: ( ESNUG 472 #5 ) You should check out VersIC from MethodICs, too
Item 9: ( ESNUG 472 #5 ) Synchronicity questions the IC Manage claims
Item 10: Steve Golson at DAC on "The Four Principles of Flow Engineering"
Item 11: Viewer's reactions to the DVcon 08 Troublemaker's Panel video
Item 12: Viewer's reactions to Wally's Ending Endless Verification video
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Trying to figure out a Synopsys bug? Want to hear how 24,298 other users
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!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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