Editor's Note: Now that all my parent's stuff is packed in a moving van
that's travelling South to their new house in Florida and their Vermont
home of 40 years is now finally empty and up for sale, normal ESNUG can
resume. Whew! It's time for this kid to get back to work!!!
- John Cooley
ESNUG/DeepChip.com
( ESNUG 472 Subjects ) ------------------------------------------ [04/30/08]
Item 1: One user's first impressions of Magma's new Titan Virtuoso-killer
Item 2: ( SNUG 07 #5 ) We got better area/timing with Incentia DesignCraft
Item 3: ( ESNUG 470 #5 ) Paul warns on the dangers of SDF-based STA flows
Item 4: One "colorful" reaction to the Rajeev Titan announcement video
Item 5: One user on IC Manage vs. Synchronicity with a Cadence interface
Item 6: an IC Manage vs. Synchronicity and an IC Manage vs. ClearCase eval
Item 7: ( ESNUG 464 #8 ) We taped out a 65 nm, 2 M instance chip with ETS
Item 8: ( ESNUG 454 #18 ) One user's first look at the new EVE Zebu-XXL
Item 9: ( ESNUG 469 #6 ) We tested Dafca's ClearBlue on a 65 nm ARM9 CPU
Item 10: Mike Santarini's farwell to covering EDA as he joins Xilinx PR
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Trying to figure out a Synopsys bug? Want to hear how 24,298 other users
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!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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