"I can't believe Cadence had the nerve to put out a press release
bragging about CDNLive having 700 attendees. We had 1,574 users
at our last San Jose SNUG. 700?... Ha! That's sooooo 90's."
- Joanne Wegener, Synopsys SNUG Program Manager
( ESNUG 469 Subjects ) ------------------------------------------ [09/27/07]
Item 1: Did Atoptech win plus Magma & Synopsys lose a big P&R benchmark?
Item 2: ( ESNUG 467 #6 ) TSMC DFM Reference Flow 8.0 is a marketing joke
Item 3: Jason on Synopsys DC-Topo vs. Cadence RTL Compiler physical stuff
Item 4: Breker Treker and their weird new "graph based verification" tool
Item 5: ( ESNUG 468 #3 ) DFM, modified LEFs, Calibre, benchmark cheating
Item 6: One user's first look at the Dafca ClearBlue silicon debugging IP
Item 7: ( ESNUG 468 #5 ) Even the French think Cliff is wrong about this!
Item 8: ( ESNUG 468 #8 ) Atrenta's response to 0-in vs. Spyglass CDC eval
Item 9: Jonathan on minimizing your density gradients inside IC Compiler
Item 10: TetraMax is tricky on sequential ATPG with synchronous memories
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Trying to figure out a Synopsys bug? Want to hear how 24,298 other users
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!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
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