"Have you considered moonlighting as a detective, John?"
- Subramanian Iyer of NuSym in reaction to
http://www.deepchip.com/wiretap/070828.html
( ESNUG 468 Subjects ) ------------------------------------------ [09/13/07]
Item 1: ( ESNUG 467 #4 ) It's trivial to see DC/Formality guidance files
Item 2: ( ESNUG 467 #13 ) PT-SI and VCS must have different timing models
Item 3: ( ESNUG 467 #1 ) Is it cheating if the LEFs pass the DRC check?
Item 4: ( ESNUG 467 #5 ) Janick caught this gotcha in his book last year
Item 5: ( ESNUG 467 #15 ) Cliff is out-to-lunch on "default_nettype none"
Item 6: ( ESNUG 467 #8 ) Richard Goering was lucky to have been fired
Item 7: ( ESNUG 467 #3 ) That DC "bad logic" bug was in version 2006.06
Item 8: ( ESNUG 467 #12 ) Mentor 0-in kicks ass vs. Atrenta Spyglass CDC
Item 9: ( ESNUG 467 #12 ) Mentor 0-in trips up vs. Cadence Conformal CDC
Item 10: ( ESNUG 467 #7 ) What happened to Arcadia Design and Mustang?
Item 11: ( ESNUG 467 #11 ) Mike Dini wrong, Synplicity FPGA revenue up 14%
Item 12: Dan's take on the Fast SPICE simulators which were shown at DAC
Item 13: User reports new hyperscaling in Mentor Calibre nmDRC is awesome
Item 14: Paul's VIM syntax files for PT 2007.06 and DC/PC 2007.03 are up!
Item 15: ( ESNUG 465 #1 ) Cadence closed testbuilder.net for low traffic
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( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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