Editor's Note: Oh, goody! I have to fly out to the San Jose SNUG next
week and I still have 10,000 work and home chores to do. Heck, I even
have 5 loads of laundry to do just so I'll have clothes to wear next
week. And now it looks like the refrigerator in our kitchen has just
died, too. Don't you just love how everything (work/home) piles up
exactly when you need the most time free to get everything done? Oy.
- John Cooley
ESNUG/DeepChip.com
( ESNUG 464 Subjects ) ------------------------------------------ [03/30/07]
Item 1: Cliff & Stu fighting over the default_nettype compiler directive
Item 2: Cooley predicted Synopsys-Magma lawsuit outcome almost exactly!
Item 3: ( ESNUG 463 #5 ) We got 2X design at less power with PowerTheater
Item 4: ( ESNUG 458 #4 ) Conformal finds DC/PhysOpt was missing 40 DFFs!
Item 5: ( ESNUG 461 #5 ) One user's Synchronicity vs. IC Manage benchmark
Item 6: E-Tools donates its own open souce CCS-to-ESCM library translator
Item 7: Cadence NC-Verilog SDF annotation won't work on bi-directionals
Item 8: ( ESNUG 461 #6 ) The Freescale first impressions of Cadence ETS
Item 9: ( ESNUG 461 #11 ) How secure is the Cadence Conformal encryption?
Item 10: ( ESNUG 443 #10 ) Is anyone else seeing these DFTMax results?
Item 11: ( ESNUG 461 #5 ) A Synchronicity user speaks up for Synchronicity
Item 12: Jason Ware -- I was away at the Cadence CPF Training last month
Item 13: ( ESNUG 458 #7 ) Synopsys response to the CCS vs. ECSM discussion
Item 14: ( DVcon05 #12 ) Conformal saw hierarchy error, Formality didn't
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Trying to figure out a Synopsys bug? Want to hear how 24,298 other users
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!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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