"By the way John, and to re-iterate my comments to you after the panel,
I thought that you did a great job bringing out some interesting issues
and doling out equally humiliating treatment to all."
- Adolph Hunter, the head of Cadence PR
( ESNUG 463 Subjects ) ------------------------------------------ [03/16/07]
Item 1: Answers from Rajeev Madhavan, CEO of Magma
Item 2: Answers from John Chilton, SVP of Synopsys
Item 3: Answers from Joe Sawicki, GM of Design-to-Silicon, Mentor
Item 4: Answers from Ted Vucurevich, CTO of Cadence
Item 5: Answers from Vic Kulkarni, CEO of Sequence
Item 6: Answers from Atul Sharan, CEO of ClearShape
Item 7: Answers from Brett Cline, the SystemC Poster Boy
Item 8: Answers from Gary Smith, Gary Smith EDA
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Trying to figure out a Synopsys bug? Want to hear how 24,298 other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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