"It seems to me DFM got funded about a year or so too soon. I think
the late adopter 65 nm guys and all the 45 nm customers will need new
approaches, but that ramp up is off in the future a bit."
- Mike Gianfagna, former CEO of Aprio
( ESNUG 459 Subjects ) ------------------------------------------ [12/14/06]
Item 1: User asks of differences between Cadence & Blaze dummy metal fill
Item 2: ( ESNUG 458 #7 ) We don't want to have to support both CCS & ECSM
Item 3: ( ESNUG 457 #1 ) Columbus extracts SPEF in 2 days; DEF in 1 hour
Item 4: ( ESNUG 458 #6 ) ye olde Verisity Axis emulator is alive & well!
Item 5: ( ESNUG 458 #2 ) Bluespec issues a chip design challenge to Forte
Item 6: ( ESNUG 458 #5 ) Precision is better & at 1/3 price of Synplicity
Item 7: customer benchmarks confirm Synopsys TetraMAX 12X speedup claims
Item 8: Cooley rightfully chastised for not looking at ClioSoft at DAC
Item 9: ( ESNUG 458 #1 ) An unofficial PrimeTime-SI vs. CeltIC conspiracy
Item 10: ( ESNUG 458 #1 ) Plus the "official" Cadence & Synopsys responses
Item 11: Gary Smith on lawsuits, Wall St., Mentor, Cadence, DFM, and 2006
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 22,739 other users
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!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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