"Over the years, I've come to the conclusion that EDA companies are the
water skier behind the boat we call semiconductors, and when the boat
stops, the skier stays upright a few moments longer, then sinks. The
boat is moving right now so Cadence and thus its management looks great.
What happens when the boat stops again? What happens when folks need
new ASIC tools for 45 nm? If Cadence's management thinks it can develop
all its own tools, history may have a hard lesson for them to learn.
Who knows? I like big Mike Fister, but the Intelish marketing stuff
from his underlings is tick'n off a lot of little startup folks; making
it very hard for them to raise VC funding. I bet all things being
equal, folks will prefer getting acquired by Cadence's competitors when
the boat stops or when Cadence execs figure out their R&D organization
doesn't build tools."
- Mike Santarini of EDN on 07/07/06 before the unmarked black
helicopters came and took him away
( ESNUG 456 Subjects ) ------------------------------------------- [07/17/06]
Item 1: A new unannounced "PrimeTime-PX" is to quietly replace PrimePower
Item 2: Cooley asks What's the Backstory behind the Oasis vs. GDSII Push?
Item 3: I need a script to translate Verplex points into Formality points
Item 4: The public link to the pocket sized Hardi VHDL syntax handbook
Item 5: 3 users on Knowlent Opal's SerDes/PCIe/XAUI electrical compliance
Item 6: ( DVcon 05 #15 ) 3 hands-on Tharas users yarp in detail on Hammer
Item 7: ( ESNUG 455 #1 ) 2 more hands-on users yarp about Apache RedHawk
Item 8: ( ELSE 06 #13 ) 2 more users on their Virtex/Precision experiences
Item 9: ( ELSE 06 #19 ) We're happy using the Magma FixedTime methodology
Item 10: ( ESNUG 446 #1 ) Yea, we found Palladium II to be 2X faster, too
Item 11: ( ESNUG 453 #2 ) "Mike and Atul don't know what we're doing!"
Item 12: A user benchmarks Custom Wire Load Models vs. "Topographical" DC
Item 13: DC 2006.06 area benchmarks; customer dumps PhysOpt for Topo DC
( ESNUG 456 Jobs Section ) --------------------------------------- [07/17/06]
Job 1: Sunnyvale, CA - Synplicity seeks senior synthesis R&D engineer
Job 2: Sunnyvale, CA - ClearShape needs a senior apps engineer
Job 3: San Jose, CA - Cadence wants an Open Access product engineer
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 22,739 other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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