Editor's Note: If you look in ESNUG 441 #12, you'll see that Brett Cline
of Forte and I had a gentleman's bet over whether or not SystemC adoption
would be over 50% in the 2005 Verification Census. (I said it wouldn't;
Brett said it would.) The loser of the wager had to wear a chicken suit
in a public setting at DAC. Here's the 4 minute video reveiling who won.
http://www.deepchip.com/demos/chicken.fhtml
Sorry about the sound for the last 30 seconds of the video; that's Abba's
"Dancing Queen" that Brett is dancing to at the Denali DAC party. :)
- John Cooley
ESNUG/DeepChip.com
( ESNUG 451 Subjects ) ------------------------------------------- [02/08/06]
Item 1: Cliff & Stu -- Help us merge Verilog & System Verilog standards
Item 2: Readers critique the "new" and "improved" Hercules announcement
Item 3: Synopsys beta testing a "pure" C-to-RTL EC tool similar to Calypto
Item 4: ( ESNUG 450 #3 ) DC 2005.09 did NOT change; it might have a bug
Item 5: Harry Foster goes to Mentor; Jasper CEO responds to competitor FUD
Item 6: ( ESNUG 450 #7 ) Find those Global Net Worst Delays in PrimeTime
Item 7: ( DVcon 05 #15 ) Three Engineers review the Eve ZeBu Accelerator
Item 8: ( ESNUG 450 #8 ) This is exactly why Synopsys created IC Compiler
Item 9: ( ESNUG 446 #11 ) Magma Blast PlanPro replacing Synopsys Jupiter
Item 10: ( ESNUG 433 #5 ) One User's Follow-Up Benchmark of DC 2005.09 XG
Item 11: ( ESNUG 450 #9 ) Press Releases & Print Ads vs. User Word-of-Mouth
( ESNUG 451 Jobs Section ) --------------------------------------- [02/08/06]
Job 1: Mountain View, CA - Jasper seeks a CAE with design/verif exper
Job 2: Mountain View, CA - Ponte seeks a senior field apps engineer
Job 3: Sunnyvale, CA - Blaze DFM is seeking a senior software engineer
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 22,739 other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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