Editor's Note: This week we'll be releasing the first videos of me and
  Pallab interviewing the EDA marketeers at DAC.  (I think "Power Tools"
  is the first category, but don't quote me on that.)  And let me tell
  you, the video camera hides NOTHING.  Is my stomach really *that* big?!?
  Oh, crap!  It's time for this fat boy to go on a diet!  Not good.  :(

                                             - John Cooley
                                               ESNUG/DeepChip.com

( ESNUG 447 Subjects ) ------------------------------------------ [09/26/05]

 Item  1: Two Users Hands-on Eval of Synplicity Certify FPGA Partitioning
 Item  2: One Designer's Evaluation of Apache RedHawk vs. Sequence CoolTime
 Item  3: Uniquifying Repeated Subdesign Instances a Pain in Olde BuildGates
 Item  4: Why Did Synopsys Bail Out on its RTL-To-Placed-Gates Methodology?
 Item  5: ( ESNUG 445 #10 ) Hey! SE vs. Astro/PhysOpt == Apples vs. Oranges!
 Item  6: A User Confirms That Those TenSilica Marketing Claims Are Legit
 Item  7: ( SNUG 04 #18 ) Three Users Benchmark Power Compiler plus XG Mode
 Item  8: Synopsys ESP Functional Equivalence Tool Kicks Ass on Memories
 Item  9: ( ESNUG 446 #2 ) Magma Responds to the User Critique of its CTS
 Item 10: ( ESNUG 446 #8 ) Denali's Proactive Response to its PCI Doc Issue
 Item 11: The Olde Wellspring Solutions VeriWell is now Free on SourceForge
 Item 12: ( ESNUG 446 #7 ) Reading Old 9-Track GDSII onto a Modern Computer
 Item 13: I Need a PrimeTime TCL Script That Finds All Paths Between 2 FFs
 Item 14: Newbie User Question on How to Draw Busses in Cadence Virtuoso-XL
 Item 15: Designer Asks for Good or Bad Experiences with InsightEDA ERC Tool
 Item 16: Stu's System Verilog Assertions Class in Boston has Openings
 Item 17: International Talk Like A Pirate Day and Clive's New Computer Book


============================================================================
 Trying to figure out a Synopsys bug?  Want to hear how 21,788 other users
    dealt with it?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
     !!!     "It's not a BUG,               
    /o o\  /  it's a FEATURE!"                 (508) 429-4357
   (  >  )
    \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
    _] [_         Verilog, VHDL and numerous Design Methodologies.

    Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
  Legal Disclaimer: "As always, anything said here is only opinion."
 The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com





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   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)