"DFT Compiler MAX is news. The news is that Synopsys is following
our technical lead. I encourage any design team interested in
DFT Compiler MAX to check out Encounter Test and other competitive
tools at the same time. We love evaluations because we win them."
- Paul Estrada of Cadence (ESNUG 442 #9)
( ESNUG 442 Subjects ) ------------------------------------------ [03/24/05]
Item 1: User Troubled That BindKey is Going Out Of Business End of March
Item 2: ( SNUG 04 #11 ) User Benchmark of Astro vs. IC Compiler (Galileo)
Item 3: Magma Offers 8 Edgy Questions on the Galileo (IC Compiler) News
Item 4: ( ESNUG 435 #7 ) A Bunch Of Happy First Encounter Users Chirp Up
Item 5: ( ESNUG 441 #4 ) Synopsys Says Magma is Lying About SI Signoff
Item 6: ( DAC 04 #40 ) Tiny Accelicon Start-up Just Happy To Be Noticed!
Item 7: ( SNUG 04 #12 ) No Thank You, Mentor Calibre; I Prefer Hercules
Item 8: ( ESNUG 434 #7 ) How To Get Nassda HSIMplus Violations in GDSII
Item 9: ( ESNUG 441 #2 ) Cadence Comments on the "DFT Compiler MAX" News
Item 10: ( ESNUG 441 #2 ) Mentor Comments on the "DFT Compiler MAX" News
Item 11: ( ESNUG 441 #2 ) Synopsys Explains its "DFT Compiler MAX" News
Item 12: ( ESNUG 441 #1 ) Two Users Benchmark ACS along with the DC XG Mode
Item 13: What Metrics Realistically Measure an ASIC Designer's Output?
Item 14: What's the Benefit of LSF Linux Hyperthreading for EDA Tools?
Item 15: My PrimeTime Generated Constrants Won't Play Nice With PrimePower
Item 16: Richard Goering, EEdesign.com, Mike Santarini, and EE Times Print
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!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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