From: Kevin Silver <kevin=user domain=denali got mom>
Hey John -
Our MemCon event has returned to San Jose on Oct 7-8. This year we're
covering memory and PCI; 20 sponsoring vendors, 25 presentations, and
some good keynoters. Registration is still free at http://www.memcon.com
Hey, do you remember that guy in ESNUG Post 400 who responded to your
"Barbara Streisand" joke about our Denali memory conference last year?
Was that guy for real? Did you ever end up talking with him?
- Kevin Silver
Denali Software, Inc.
> From: Chris North <Chris.North@pridepost.com>
>
> Sir,
>
> I am the San Francisco founding member of the Barbara Streisand
> Fan Web Ring. Your "bad joke" reference to Ms. Streisand is
> humorless and offensive. Barbara is not a joke. In view of your
> insolence, I have put the word out so that none of the Bay Area
> Streisand impersonators will work your conference. I shall be
> contacting your sponsors to inform them of our boycott of their
> products and services. Your hate speech shall not stand.
>
> - Chris North, founder
> Barbara Streisand Fan Web Ring San Francisco, CA
> (from ESNUG Post 400)
Editor's Note: To answer Kevin's question, after I published that letter
I called the two "C. Norths" listed in the San Francisco phone book.
They had no knowledge of any Barbra Streisand web ring. So it was a joke.
I contacted 27 suspects, known jokers & secret jokers in EDA, asking them
if they had sent me that email. Of those 27 suspects, 26 replied back
within the day saying they didn't do it. There's only one person who I
emailed 3 different times who never replied back. And this person has a
long history of replying back to the emails I've sent him. Just these 3
times, he oddly didn't reply.
That person is Wally Rhines, the CEO of Mentor, a well known prankster.
When I pull the facts together, they all point to Wally, too. His letter
talks about "contacting your sponsors"; at that time the one big buyer of
banner ads on DeepChip was Mentor -- something Wally would have been aware
of then. Wally is from Texas. He'd spell "Barbara" like "Barbara Bush";
as its spelled in this letter. The correct spelling for Streisand is
"Barbra". In addition, Wally is from the generation that loved Steisand;
she's a natural reference for him. He may not own her records, but he'd
know her music well. And my final proof is the actor who plays Mr. Big
in "Sex and the City" is Chris North. That's a subtle Wally way of saying
"this email came from a Mr. Big"; the "Mr. Big" of Mentor.
Wally's fingerprints were all over this. Prank well done! :)
- John Cooley
the ESNUG guy
( ESNUG 418 Subjects ) ------------------------------------------ [09/30/03]
Item 1: ( ESNUG 415 #1 ) A Denali vs. DW Mem Controller Bake Off (Part 2)
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
( ESNUG 418 Item 1 ) -------------------------------------------- [09/30/03]
Subject: ( ESNUG 415 #1 ) A Denali vs. DW Mem Controller Bake Off (Part 2)
> Enclosed are the detailed Denali user responses. Public spankings aside,
> that's where the interesting tech story is here, though. In a later ESNUG
> I'll send you the Synopsys DW mem IP user responses to the same questions.
>
> - John Cooley
> the ESNUG guy
From: John Cooley <jcooley=user domain=theworld hot palm>
As I promised in ESNUG 415 #1, here's the DesignWare mem controller and
memory models user responses to my Denali vs. DW Mem Controller bake off.
There's one added question here that I didn't ask the Denali people and
that was "Did you use the DesignWare memory models? What was your
experience with them? How do they compare to Denali's memory models?"
So you might want to keep track of whether the user response is about
DW mem controller (memctrl) or the DWMM (DW memory model).
- John Cooley
the ESNUG guy
P.S. Normal ESNUG returns next week!
---- ---- ---- ---- ---- ---- ----
> What type of memory are you using? What speed is your memory running at?
> What is your data path width? What process are you designing for?
TSMC 0.13, Internal SRAM and external SDRAM, 120 MHz, 32 bits
- Parag Bhatt of Airgo Networks
TSMC 0.13 um, Sync-SDRAM, 120 Mhz, 32 bits
- Subbu Muddappa of Woodside Networks
TSMC 013 G, DDR-SDRAM, FLASH, internal SRAM
internal SRAM @ 300 MHz, DDR @ 200 MHz, Flash ~ 10 MHz
128 bits
- [ An Anon Engineer ]
0.13um, async SRAM, SSRAM, FLASH.
The SSRAM will run at 100 Mhz however the memctl runs at 200 Mhz.
32 bits.
- Jacob Guttman of Nortel Networks
SiS 0.18 um, DDR-SDRAM, DDR-II SDRAM, DDR-333, DDR-400, DDR-II 533, 32 bits
- [ An Anon Engineer ]
Probably TSMC 0.18 um, SDRAM, Flash, ~150 Mhz, 32
- Tony Sauvageau of Mitsubishi Electronics
I'm using ST H9 process (0.13 um).
I use Flash and SDR-DRAM.
To avoid speed problem on the PCB, I've been chosen 80 MHz.
I'm using 16 bits Flash and SDRAM however our AHB bus is 32 bits.
- Mauro Bosco of STmicroelectronics
TSMC 0.18 um compatible
internal SRAM, external SRAM, Flash, SDRAM, DDR-SDRAM
100 MHz
32 bit AHB bus width
- Bernd Meyer of National Semiconductor
Xilinx FPGA Virtex II, SDR-SDRAM, Flash, 33 MHz. 32 bits for SDRAM and
8 bits for Flash.
- [ An Anon Engineer ]
TSMC 0.18 um, DDR-SDRAM, 200 MHz clk (1.6 GB/s), 32 bits
- Steven Hanna of Genesis-Microchip
UMC 0.18
SDR-SDRAM, FLASH, SRAM
107 MHz
SDRAM-32, FLASH-16
- Eugene Grayver of Innovics Wireless, Inc.
Infineon 90 nm
Embedded Single Port Ram / Embedded Dual Port RAM / Embedded ROM
Note that these are compilers (not standalone memories).
From 2 bits up to 128 bits.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
> What memory devices are supported? (i.e. up to N micron 256M x 16 devices)
32M micron SDRAM and 512K flash
- [ An Anon Engineer ]
1 256 MByte memory
- Bernd Meyer of National Semiconductor
We have 5 chip-selects each can support up to 2MByte. For now, I'm using just
one 256k x 32 SYNCBURST (Micron).
- Jacob Guttman of Nortel Networks
1 x 4mx32 (128 Mb)
1 x 8mx32 (256 Mb)
2 x 8mx16 (2x128 Mb)
2 x 16mx16 (2x256 Mb)
- Steven Hanna of Genesis-Microchip
We are trying to support a wide variety of industry available devices:
micron, Samsung, Hynix, ... etc.
- [ An Anon Engineer ]
32M device
- Parag Bhatt of Airgo Networks
Not really decided.
- Tony Sauvageau of Mitsubishi Electronics
Micron 128 Mb x32
- Subbu Muddappa of Woodside Networks
256M x 8
- [ An Anon Engineer ]
The SDRAM is the mt48lc4m16a2 (8M x 4 x 16 bits) and the Flash is the
am29bl802c (512K x 16 bit).
- Mauro Bosco of STmicroelectronics
---- ---- ---- ---- ---- ---- ----
> Did the DW mem controller meet your performance requirements? Was it
> optimal for your application?
Yes.
- Subbu Muddappa of Woodside Networks
It is acceptable. Performance was not an issue.
- Eugene Grayver of Innovics Wireless, Inc.
Yes.
- [ An Anon Engineer ]
It meet our performance requirements. What is not supported is the
possibility to drive SDRAM with a clock that is not the memctl one.
- Mauro Bosco of STmicroelectronics
Yes it met our needs. We wanted to use ZBT SSRAM but I had to settle for
the older "Syncburst" type. I had to add a bit of glue logic to make the
memctl work with SSRAM since it is primarily designed to work with async
memories.
- Jacob Guttman of Nortel Networks
DW controller met our performance needs for the SRAM and Flash controllers.
It fell short of meeting our DDR target.
- [ An Anon Engineer ]
yes
- Bernd Meyer of National Semiconductor
Yes, it meets my performance requirements.
- [ An Anon Engineer ]
Yes.
- Parag Bhatt of Airgo Networks
---- ---- ---- ---- ---- ---- ----
> Did you use the DesignWare memory models? What was your experience with
> them? How do they compare to Denali's memory models?
Used Denali memory models, they seem to be more accurate.
- Bernd Meyer of National Semiconductor
I use the DWMM model, not the DW mem controller.
If you have DW license, you can use it without additional payment. It also
has several testbench commands to observe the result. Besides the HDL, it
also provide the VERA interface.
But we can not use the user-defined timing for some cases.
I did not use the Denali, but maybe in the future.
- [ An Anon Engineer ]
We haven't used Denali memory model in this company; I couldn't compare
these two. Since the DesignWare memCTL is closely integrated with the
memory, it was easy for us integrate. We didn't run into any problems
that one does while integrating models into a verification flow.
- Subbu Muddappa of Woodside Networks
Yes, I used the DW memory models. It was very convenient to use DW memory
models since the DW-memctl came with a wrapper wired for the chosen memories
(selected via coreConsultant as part of the configuration process of the
DW-memctl.)
I did not compare Denali's memory models to Synopsys' memory models.
- Jacob Guttman of Nortel Networks
I tried to use the DesignWare memory models, but didn't succeed.
- [ An Anon Engineer ]
We did not use the Synopsys DW memory models.
- Parag Bhatt of Airgo Networks
In terms of usage, they have the same functionalities as the Denali ones.
- [ An Anon Engineer ]
Yes, we used DesignWare memory Models. Overall, it was easy to use. The
only thing that we preferred with the Denali memory models is that we were
also able to use them on the PC platform running windows.
- Steven Hanna of Genesis-Microchip
We've used the models to run simulations as well as Denali's. Our
verification team feels that the Denali's models can link with their
Vera environment setup much easier.
- [ An Anon Engineer ]
I'm using DesignWare memory models. The experience is quite good, but I
cannot compare them to Denali's models because I don't know those models.
- Mauro Bosco of STmicroelectronics
No, we used plain VHDL models.
- Eugene Grayver of Innovics Wireless, Inc.
---- ---- ---- ---- ---- ---- ----
> Did the DW mem controller support your synthesis/simulation/STA flow?
I just tried a quick synth of the controller just to see that it will run at
200 Mhz, and it did meet the requirement. However, I am not done yet, I'll
have to get back to synth soon.
- Jacob Guttman of Nortel Networks
Not very well -- we had to synthesize to gate level GTECH netlist for
sim. However, it works.
- Eugene Grayver of Innovics Wireless, Inc.
Yes for the SRAM & Flash. Not DDR.
- [ An Anon Engineer ]
Haven't went through synthesis/timing yet.
- Tony Sauvageau of Mitsubishi Electronics
Yes, but we ran into problems while using Cadence NC-Verilog and had to
use a gate-level netlist memCTL to proceed with RTL simulation. We didn't
have any timing issues, even though we would liked to have an extra pipeline
in the AHB interface.
- Subbu Muddappa of Woodside Networks
yes
- Bernd Meyer of National Semiconductor
Yes.
- Parag Bhatt of Airgo Networks
Yes.
- [ An Anon Engineer ]
Regarding simulation I'm using Cadence (NC-SIM). Because the memory
controller RTL is encrypted and then usable only by synopsys tools, I have
to do a simulation using a GTECH mapping.
Regarding synthesis and STA, I'm not working on it but I don't see big
issues because we use the Synopsys tools.
One point that seems to generate problems is a porting of the system to
an FPGA. We used Synplicity for the core and until now Synopsys has not
yet suggested to us how can map the overall system.
- Mauro Bosco of STmicroelectronics
---- ---- ---- ---- ---- ---- ----
> Which P&R tool do you use? Did it have any troubles with the controller?
> What RC extraction and DRC/LVS tools did you use? Did they have any
> troubles with the DW mem controller? Which DFT tools did you use? Find
> any mem controller issues?
First Encounter -- no problems. The documentation for SDRAM timing
could be improved -- we made a mistake the first time. Test Compiler had
no issues.
- Eugene Grayver of Innovics Wireless, Inc.
Astro, no trouble with the controller (not more than usual).
StarRC-XT, no trouble
DFT not run yet.
- Bernd Meyer of National Semiconductor
Magma. Don't know.
Cadence Affirma. No.
Mentor Fastcan. No.
- [ An Anon Engineer ]
The vendor will be doing DFT for us. I'm not sure what tool they intend to
use. I may insert the scan chains myself. We don't have external mem-BIST.
We are not there yet, but our ASIC vendor will be using PhysOpt.
I noticed that not all data and control signals are "flopped" going to the
memory ... (e.g. output-enable, etc.)
- Jacob Guttman of Nortel Networks
Xilinx ISE. The previous version of Xilinx ISE (4.2i) reported errors with
the controller, therefore I upgraded to Xilinx ISE 5.1i to get around the
problem.
- [ An Anon Engineer ]
FPGA, Xilinx timing issues.
Cadence for DRC/LVS, no issues.
No DFT issues.
- Parag Bhatt of Airgo Networks
We used First Encounter + SE. SynTest.
I did not use DW Memory Controller, but maybe in the future.
- [ An Anon Engineer ]
Magma tools, Blastwhatever. Sequence tools and Magma tools. Mentor
FastScan. No EDA troubles specific to the DW mem controller.
- Subbu Muddappa of Woodside Networks
Cadence FE, no it did not have trouble with controller.
We are not that far but we would be using xCalibre.
We are planing to out source the DFT work. We haven't run into any
problems yet.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
> Did the DW mem controller require any special I/O pads? Did Synopsys
> provide you with help in this area?
No. We are using TSMC 4mA (I/O) pads. We had some issues with the output
timing, but with controlled(steps of 0.5ns) delayed clock to the SDRAM, we
were able to close timing.
- Subbu Muddappa of Woodside Networks
No special I/O pads are required, but we have to add some glue logic
(a read pipe) in order to reduce timing problem. I had some issues
regarding the Flash solved thanks to Synopsys.
- Mauro Bosco of STmicroelectronics
We only used SDR, no special pads required.
- Eugene Grayver of Innovics Wireless, Inc.
The DDR would have required SSTL-II pads. I did not ask them for any help
in the area.
- [ An Anon Engineer ]
No & no. The pads are more of an issue with the type of memory we use
(2.5 vs 3.3V) and what is available from the chip vendor.
- Jacob Guttman of Nortel Networks
SSTL2 IO's for DDR-SDRAM, designed our own
- Bernd Meyer of National Semiconductor
No.
- [ An Anon Engineer ]
No special IO pads.
- Parag Bhatt of Airgo Networks
---- ---- ---- ---- ---- ---- ----
> Did the controller meet Synopsys' size estimate? (i.e. number of gates)
Trial synthesis a couple versions ago matched the size estimate.
- Tony Sauvageau of Mitsubishi Electronics
It was a little bigger than we had anticipated, by about 10%. But the ease
of integration and clean verification environment, offset the 10% increase.
- Subbu Muddappa of Woodside Networks
Did not check this.
- [ An Anon Engineer ]
yes
- Bernd Meyer of National Semiconductor
Yes.
- Eugene Grayver of Innovics Wireless, Inc.
Yes
- [ An Anon Engineer ]
More or less, at first look I recall thinking that it was rather large, I'll
know more when I get back to synth.
- Jacob Guttman of Nortel Networks
Yes, +/- 5%.
- Parag Bhatt of Airgo Networks
yes
- Mauro Bosco of STmicroelectronics
---- ---- ---- ---- ---- ---- ----
> Did the Synopsys DW mem people provide good customer support?
Great, but appears to be getting slower.
- Eugene Grayver of Innovics Wireless, Inc.
Yes.
- Subbu Muddappa of Woodside Networks
Yes
- [ An Anon Engineer ]
Not really. Needed to bug them a lot.
- Parag Bhatt of Airgo Networks
Yes.
- [ An Anon Engineer ]
yes
- Bernd Meyer of National Semiconductor
Yes. (Not specfically for memory controller, just DesignWare in general.)
- Tony Sauvageau of Mitsubishi Electronics
For DW MacroCell, there are too many bugs. Revised many times.
- [ An Anon Engineer ]
On the DW-memctl it was excellent! But maybe I was lucky to get a good
app engineer.
- Jacob Guttman of Nortel Networks
yes
- Mauro Bosco of STmicroelectronics
---- ---- ---- ---- ---- ---- ----
> Did you tape-out? Did you get to silicon? production? How many chips?
Yes. Not in full production yet, we are sampling to customers at this
point of time.
- Subbu Muddappa of Woodside Networks
Yes, thousands.
- Eugene Grayver of Innovics Wireless, Inc.
Yes, tape-out. Production in 1000s.
- Parag Bhatt of Airgo Networks
Not yet.
- [ An Anon Engineer ]
no
- Bernd Meyer of National Semiconductor
Not yet. couple of months away.
- [ An Anon Engineer ]
No
- Tony Sauvageau of Mitsubishi Electronics
Not yet.
- Mauro Bosco of STmicroelectronics
No.
- [ An Anon Engineer ]
Not yet.
- Jacob Guttman of Nortel Networks
Not yet.
- Steven Hanna of Genesis-Microchip
---- ---- ---- ---- ---- ---- ----
> Were there any surprises you had wished you'd know about beforehand?
I could have designed the Mem controller myself for less area and more
control in fixing issues or working around them.
- Parag Bhatt of Airgo Networks
More details on SDRAM timing -- constraint generation would help.
- Eugene Grayver of Innovics Wireless, Inc.
No. Not yet.
- Subbu Muddappa of Woodside Networks
The orignal version I got has a bug regarding SDRAM refresh and I had to
upgrade it.
- [ An Anon Engineer ]
So far they are just fine. No problems in simulation.
We haven't actually used the designware mem controller in a real product,
but are just creating an ARM simulation environment (that could possibly go
into a later product). We're using the DW mem models. I've never used
Denali Databahn memory controllers, so I cannot compare versus DesignWare.
No problems with simulation (VCS). Haven't tried synthesis/STA.
- Tony Sauvageau of Mitsubishi Electronics
Not yet.
- [ An Anon Engineer ]
Not yet.
- Jacob Guttman of Nortel Networks
Too many bugs in DW_memctl!
- Bernd Meyer of National Semiconductor
No
- [ An Anon Engineer ]
nothing special
- Mauro Bosco of STmicroelectronics
Not yet.
- Tony Sauvageau of Mitsubishi Electronics
---- ---- ---- ---- ---- ---- ----
> Licensing? What type of NDA's contracts, royalties were required from
> the Synopsys DW mem controller IP people you dealt with?
Just the regular DesignWare license and DesignWare regression license.
- Subbu Muddappa of Woodside Networks
If you have DW license, you can use DW mem model without additional payment.
- [ An Anon Engineer ]
Whatever was already in place between Synopsys and Nortel Networks.
- Jacob Guttman of Nortel Networks
Covered by DesignWare license, no NRE or royalties
- Bernd Meyer of National Semiconductor
Standard NDA
- Parag Bhatt of Airgo Networks
With DW, there is a licence fee as with Denali. I am not aware of any
royalties with either.
- [ An Anon Engineer ]
The controller is free -- main reason we picked it.
- Eugene Grayver of Innovics Wireless, Inc.
Licenses are available at ST.
- Mauro Bosco of STmicroelectronics
---- ---- ---- ---- ---- ---- ----
> What was the main value of the Synopsys DesignWare memory IP solution?
> Why did you choose it over the Denali solution?
Mainly it was a cost issue. We already owned the Synopsys DesignWare
license, and did not make sense to continue using the Denali solution if
we were already paying for a memory model solution in DesignWare.
- Steven Hanna of Genesis-Microchip
Time to market, no extra cost
- Bernd Meyer of National Semiconductor
Main advantages:
- We (as memory compiler developers) are the ones doing the changes in our
models. For Denali, we need them to do the changes -> loss of time and
less control on quality.
- We keep exactly the same behaviour/warnings as our "normal" VHDL/Verilog
- Easy integration in our memory compiler.
Time to change and test one compiler: less than one day.
- [ An Anon Engineer ]
I guess the main value of their mem models (not their mem controller) was
that it is included with the licences we already purchase from Synopsys.
Of course, it also seems to do the job well and is easy to use.
- Tony Sauvageau of Mitsubishi Electronics
We already bought the Designware Foundation, it just came with it.
- Parag Bhatt of Airgo Networks
We chose the Synopsys DW mem controller for SRAM and Denali for the DDR.
Denali does not ofer SRAM or Flash controllers.
My experience with the Denali controller is that the design team there
is a bit overloaded and need to slip delivery date occasionally. Their
controller is in a good shape, but we still found few bugs with our
configuration.
Customers might not encounter the same problems we had if they were
using a vannilla controller that has been produced before.
- [ An Anon Engineer ]
We wanted to get all the IPs from one company and we had good results
from Synopsys. So we used Synopsys solution.
- Subbu Muddappa of Woodside Networks
I chose it because my company has a global license for this IP.
- [ An Anon Engineer ]
As I said, I did not evaluate Denali but the main value would be that with
Synopsys DW it was a "one stop shopping place". I got all of my AMBA-bus
components, models and verification environment (bus models and monitors,
etc.) in addition to the memory models and the memctl.
I got started right away since we had everything I needed on our CAD tree.
(We have not signed up the NDA with ARM yet...)
- Jacob Guttman of Nortel Networks
I'm not familiar to the Denali solution and I'm cooperating with Synopsys to
evaluate the AMBA DesignWare. For this reason when we needed a memctl. I
choose the DesignWare one.
- Mauro Bosco of STmicroelectronics
We did not use the sim models.
- Eugene Grayver of Innovics Wireless, Inc.
Only DW mem model:
It has several testbench commands to observe the result. Besides the HDL,
it also provide the VERA interface.
I did not use the Denali, but maybe in the future.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
> Would you use the DW mem solution again? Would you recommend it to
> others?
yes, yes
- Bernd Meyer of National Semiconductor
Yes, Yes.
- [ An Anon Engineer ]
I would definitely use the DesignWare solution, except the source should
be made available as we will be restricted to run only with VCS and we
can not go to any other simulators. This is a big deal for us, probably
because of this we might design a mem controller ourselves.
- Subbu Muddappa of Woodside Networks
Yes, the only negative is the fact that we must synthesize to netlist to
simulated.
- Eugene Grayver of Innovics Wireless, Inc.
I would think twice and if possible, avoid the DesignWare mem controller.
It is difficult to work with any IP that you do not have access to the
source code.
- Parag Bhatt of Airgo Networks
Sure. I'd certainly tell someone that their mem models available and
suggest they look into it.
- Tony Sauvageau of Mitsubishi Electronics
Yes, I think it is a good solution when IPs are not available on our site.
- Mauro Bosco of STmicroelectronics
I may use the Designware solution again.
- [ An Anon Engineer ]
Yes to the memory model. Did not use the DW mem controller.
- Steven Hanna of Genesis-Microchip
Yes. We want to deliver VHDL/Verilog Designware models in our next
release (Q2 2003).
- [ An Anon Engineer ]
Definitely.
- Jacob Guttman of Nortel Networks
I will use the DWMM again, and I think the DWMM will be better in the
future. I recommend the DWMM if you have DW license. If I use DW Memory
Controller in the future, I will try to use it with the DWMM.
- [ An Anon Engineer ]
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 17,088 other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@TheWorld.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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