Found On First Spin ICs/ASICs:
Functional Logic Error ###################### 43%
Analog Tuning Issue ########## 20%
Signal Integrity Issue ######### 17%
Clock Scheme Error ####### 14%
Reliability Issue ###### 12%
Mixed Signal Problem ##### 11%
Uses Too Much Power ##### 11%
Has Path(s) Too Slow ##### 10%
Has Path(s) Too Fast ##### 10%
IR Drop Issues #### 7%
Firmware Error ## 4%
Other Problem # 3%
Overall 61% of New ICs/ASICs Require At Least One Re-Spin.
Source: Aart de Geus, Chairman & CEO of Synopsys, during
today's Boston SNUG keynote address
( ESNUG 417 Subjects ) ------------------------------------------ [09/08/03]
Item 1: ( ESNUG 416 #8 ) Another User Sees Bad PhysOpt Quality Of Results
Item 2: ( ESNUG 416 #5 ) Cadence CeltIC & Astro Xtalk Repair Capabilites
Item 3: ( ESNUG 416 #6 ) Magma BlastFusion With Mentor Calibre DRC/LVS
Item 4: User Asks For Flexlm EDA License Tracking & Useage Scripts/Utility
Item 5: ( ESNUG 416 #2 ) Astro Hierarchy Preservation After The Fact
Item 6: ( ESNUG 407 #1 ) 0-in, Averant, Real Intent, Jasper, Verplex
Item 7: Synopsys PrimeTime-SI vs. Cadence CeltIC + Standard PrimeTime
Item 8: ( ESNUG 410 #10 ) Synopsys Caught Spreading Vera/NC-Sim Speed FUD
Item 9: Two Users Review Mentor's New Precision FPGA Tools vs. Synplicity
Item 10: ( ESNUG 416 #3 ) AMD's Opteron & Intel's Influence Over Synopsys
Item 11: One User's First Impressions Of Nassda's Hanex From Its DAC Demo
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
( ESNUG 417 Networking Section ) -------------------------------- [09/08/03]
Santa Clara, CA -- Mobilygen seeks physical design, verification, & ASIC
design engs. New VC funding! monsen=user company=mobilygen spot calm
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 17,088 other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@TheWorld.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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