Subject: (Part 2) "Attack Turkeys" & Massachusetts Tax Dollars At Work
Back at their TV station, the news people cleverly edited their video
to not show the turkeys being chased by the TV reporters -- but to only
show "innocent" TV reporters being "attacked" by an obviously crazy
turkey. Once broadcast, the news set off a weird chain of events.
Local kids and curiousity seekers came to see "killer turkeys." CNN
loved the story and added it to their U.S. news report. People started
coming from 100's of miles away to see "killer turkeys." Holliston
housewives, terrified with visions of rampaging turkeys assaulting their
poor, defenseless children, flooded the town police with worried phone
calls. The Massachusetts Evironmental Police came by and said that the
turkeys where a half-wild/half-domestic breed that had to be killed or
caught -- so they don't interbreed with the overall turkey population.
The Town Selectmen voted to pay $20,000 for a professional trapper to
catch the turkeys without guns (he set up big cage traps.) Naturalists
started messing with the cage traps to protect the turkeys; causing the
trapper to call the police to protect his traps. The political enemies
of the Town Selectmen wrote embarrassing letters to the town newspaper
saying $20,000 to trap turkeys was absurd and a sign of mismanagement.
And then, not too much later, the turkeys suddenly just disappeared!
- John Cooley
the ESNUG guy
( ESNUG 250 Item 1 ) -------------------------------------------- [9/6/96]
Subject: ( ESNUG 248 #8 249 #2) Timing Paths Through A Bi-Directional Bus
> 2) Nuke the bidi buses. That's what we eventually did. We were able to
> make a floorplan that had contained the bidi busses in a relatively
> small area, so we restructured it to use muxes instead of tristate
> busses. It ended up much cleaner, and as a bonus the time to do
> update_timing went down by a factor of about 8.
From: Bill Armstrong <army@hlds.com>
John,
Irregardless of whether or not you can get Synopsys to time the design the
way you want, there are other issues to consider depending on how well your
silicon vendor characterizes and models them:
1) Does your vendor's library model the output (drain) load of the
3-state driver? Some vendors do not consider this load in their
models because it is more difficult to characterize, they may
think it to be insignificant compared to the gate (poly) load or
they just overlooked it. What ever the reason, if it is not
there and you have several 3-state drivers attached to the same
net, as is typically the case, simulation accuracy will be
reduced.
2) Does your vendor accurately characterize the turn off time of the
driver, or the time the enable signal propagates through the gate
and the driver actually lets go of the bus? Also, how well is
the skew between enable signals controlled?
3) Routing of 3-state signals is not handled well in most place and
route tools. Typically 3-state cells are small with no feed-thrus
for other signals to route over them. Multiplexers are bigger
and usually have a feedthru or two. 3-state nets with a number
of drivers are usually place in close proximity to each other
because they are highly connected creating a spaghetti, or rats
nest, type of situation and making routing much more difficult
than if there was a single multiplexer.
Now your vendor may handle all of these situations perfectly and you
may have never encounter these problems. That's great and by all
means use 3-state drivers. However, if your planning on targeting
several different vendors with this design, the likely hood of running
into one or more of these situations increases dramatically. In my
opinion, for what it's worth, designing for manufacturability is much
more important than having a slick way for the synthesis tool to
time the design.
My experience suggests avoiding internal 3-state drivers altogether.
- Bill Armstrong
High Level Design Systems
( ESNUG 250 Item 2 ) -------------------------------------------- [9/6/96]
Subject: ( ESNUG 249 #7 ) What's The Best Way To Synthesize Multipliers?
> Could you share your multiplier design experience using RTL Verilog code
> and Synopsys? I know "X=A*B;" doesn't work well. I also know that there
> are people who hand instantiate Booth decoders and adders. What is the
> most efficient and flexible way to synthesize a multiplier?
From: mgandhi@indusinc.com (Milan Gandhi)
Hi, John, in my experience:
DO: constrain multipliers *accurately* (don't over or under constrain)
and Design Compiler will do a good job meeting that constraint.
DON'T: flatten or remove hierarchy in a design with a multiplier.
Also, you will need a DesignWare licence to get the faster multipliers.
- Milan Gandhi
Indus Consulting Services, Inc
( ESNUG 250 Item 3 ) -------------------------------------------- [9/6/96]
From: Andrew Frazer <Andy.Frazer@idt.com>
Subject: I Need Better Control Of Synopsys SDF File Generation
Hey, John, I have a question about SDF files.
We are trying to use Synopsys for our pre-layout delay calculator. We use
Synopsys to write out the SDF file, then we back-annotate the SDF file into
Verilog and/or Ikos.
The problem is that Synopsys writes out an SDF file where all three timing
parameters (min/typ/max) are identical because it calculates the delays
based on the last "set_operating_conditons" command.
We want to write out one SDF file where "min" delays are calculated
with "best_case_commercial" operating conditions, "typ" delays are
calculated with "typical_case" operating conditions, and "max" delays
are calculated with "worst_case_conditions".
The current workaround is to write out three different SDF files, each of
which is calculated with under different operating_conditions. Any ideas?
- Andy Frazer
Integrated Device Technology
( ESNUG 250 Item 4 ) -------------------------------------------- [9/6/96]
From: <hallums@graphx.eng.pko.dec.com> (Tyrone Hallums)
Subject: What Are The Best Layout Tools In Today's Market?
Hello John,
Which automated layout tools would you recommend between Mentor, Cascade,
Avant!, Cadence, etc? I used the Epoch tools from Cascade in school, but I
want to hear about the other vendors who make similar layout tools.
- Tyrone Hallums
Digital Equipment Corporation
( ESNUG 250 Item 5 ) -------------------------------------------- [9/6/96]
Subject: ( ESNUG 248 #5 249 #6 ) FSM Treatment Doesn't Seem Coherent
> As for your question of increasing performance, my first post still holds
> about one-hot and gray codes. For one hot, your mealy or moore output
> should be the state, and since there is one flip flop per state, you
> should not need wide combinatorial decodes to get valid state transitions.
> Take your circuit into the FSM compiler and perform a one-hot synthesis
> --that should give you the fastest output.
From: peer@iis.fhg.de (Dieter Peer)
I did some more evaluation on my design, and - for your information - I got
much worse results using one-hot. Best results in terms of speed I got
using some specific 4- or 5-bit state assignments. The reason is that my
ASIC lib has maximum 4 input gates (6 for complex gates). In order to
decode an 8-bit state, Synopsys seems to not only use the ones of its
state flip-flops but also some of the zeros.
I only partially agree. As long as the FSM is a straightforward counter or
shift register, you are right. But in a FSM usually there are lot of
non-incremental transitions needed, depending on the inputs (like 3->6,
7->1, 8->8 etc.). So the resulting netlist for that FSM would never be a
shift register or counter.
> Now, let's say you changed the order of the machine from ABCDEFGH to
> HACFGEBD, the machine would no longer transition in the order of a shift
> register, resulting in a differenct circuit.
I do not agree. It still IS a shiftreg in your terminology, just the ORDER
of the flipflops changes the same way as you swap the colums of the
assignment order from ABCDEFGH to anything.
John, I am still waiting for an explanation, why identical state coding with
variations of the ORDER of state-vector-assignment for a FSM produces
different synthesis results using synopsys software. Due to Synopsys
information it is probably related to a starting point problem in
synthesis. But this would mean, that for state machines using (e.g. one-hot
coding) it is worth trying different variations of one-hots, as some of
these are very-hot and others only one-warm.
- Dieter Peer
Fraunhofer-Gesellschaft
---- ---- ---- ---- ---- ---- ---- ----
From: "M. Arnold" <marnix@hydra.et.tudelft.nl>
Hi John,
In ESNUG 249, Ted Boydston and Dieter Peer are, at one point, talking
about "grey" and "gray" codes. I was taught that the only correct
spelling is "Gray", after Frank Gray who first patended their use in
1953 (F. Gray, "Pulse Code Communication", U.S. Patent 2 632 058,
March 17, 1953). Just my nitpicking $.02. :^)
- Marnix Arnold
Delft University of Technology
---- ---- ---- ---- ---- ---- ---- ----
Dieter Peer wrote: (in ESNUG 248 Item 5)
> I understand that I get quite different results when using different
> state assignments. Do you know an explanation, why the results also
> differ, if I change only the ORDER of my state vectors? Could I
> perhaps also get better or worse results, if I would change the order
> of my entity ports in the VHDL description from alphabetically to
> (whatever)?
From: Martin Radetzki <radetzki@offis.uni-oldenburg.de>
Dear John,
The mapping between states and code bits is often defined by a code matrix,
where the rows correspond to the states and the columns to the code bits.
In the literature it is stated that "permuting of columns does not affect
the cost of a realization, because it is equivalent to relabeling flip-flop
variables." [Michel, Lauther, Duzy (Eds.); The Synthesis Approach to Digital
System Design; Kluwer 1992].
So I think, Dieter is right to expect Synopsys to produce equivalent logic.
But as I have read (sorry, can't find the source), they calculate random
generator seed values from the Verilog/VHDL code in order to ensure "same
code, same logic" when applying random strategies. This might be an
explanation for the differences in synthesis results when changing the
ENUM_ENCODING attribute or the order of entity ports in the source code.
- Martin Radetzki
OFFIS Research Institute
[ Editor's Note: Martin, you read about how Synopsys generates "random"
seeds based on source code back in 3/3/93 in ESNUG 180 ! - John ]
( ESNUG 250 Item 6 ) -------------------------------------------- [9/6/96]
From: Ross Swanson <swanson@est07.bwi.wec.com>
Subject: I *Always* Want "Selecting Critical Implementations"
John,
If I synthesize a 20 bit adder I get around 30ns performance, but if I
use set_max_delay and compile, the timing is reduced to just over 7ns.
This option enabled 'Beginning Resource Allocation' to use 'Selecting
critical implementations', and so a Carry-Look-Ahead adder was picked
from DW01, instead of a ripple adder.
Why didn't I get the fastest adder from DW01 without set_max_delay?
And what if the adder is buried around other logic, how do I use
set_max_delay so that I don't get a ripple adder but Carry-Look_ahead?
Or is there some secret Synopsys switch known only to the High Priests
of Synopsys that will always enable 'Selecting critical implementation'?
- Ross Swanson
NorthropGrumman
( ESNUG 250 Item 7 ) -------------------------------------------- [9/6/96]
Subject: ( ESNUG 249 #5 ) HELP! I've Got CLI or SWIFT or VSS Memory Leaks!
> I'm encountering a mysterious memory leak in my simulation environment.
> My testbench in VSS uses RTL VHDL, SmartModels, and the CLI C
> interface. I'm running Sun/SunOS4.1.4. There is a memory leak
> somewhere -- the simulator process starts out with a size of ~100
> megs, but after running overnight (about 15ms with a 1ns timebase and
> a 30ns system clock) the process grows to over 600 megabytes!
From: blogs@telxon.com (Brian Logsdon)
Yep! I have seen memory leaks as well, but they have been related to
problems in OpenWindows. I don't ever recall a memory leak problem in VSS,
but if you have WAVES running, that could really suck the memory up.
Check with your sysadmin to see if you have all of the OpenWindows patches
that you need.
- Brian Logsdon
Telxon Corporation
---- ---- ---- ---- ---- ---- ---- ----
From: Pier Garino <Pierangelo.Garino@cselt.stet.it>
John,
We experienced the same memory problem in June, when we tried to use the
release V3.4a of VSS. A STAR was issued, but up to now this has not been
solved yet.
We have nearly the same environment as depicted by Ken, i.e. we use a
testbench with RTL synthesizable descriptions + a Smartmodel (rel R40a) of
an SDRAM component (upd4516161).
Until we used the V3.3b VSS version we were able to simulate our testbench
up to more than 500 ms of simulation (28ns clock period - 1ns resolution
got more than 3 days of run time on a Sparcstation 20) without noticing any
problem. The vhdlsim process just took some tens of MBytes.
After the V3.4a announce, we decided to use it to shorten the simulation
times -- faster simulation was one of the improvements claimed by Synopsys.
But when we went to the V3.4a, our simulations just crashed overnight! We
looked into the code, without finding any explanation. The crash appeared on
all the stations and operating systems we tried to use (Sparcstations with
SunOS 4.x, Ultrasparcs with Solaris 2.5, hp700 with HP-UX!) The problem was
always an abnormal increase of the process memory size, which doubles every
time (except for an initial 'offset' value) up to more than 2GBytes, but
still not enough to finish our simulations!!
We then contacted our local Synopsys Support Center (Italy), who asked for a
test case to be analysed. We were able to provide a very compact test case,
where there is just a component instantiated within the testbench (stimuli
supplied directly through a wif file), i.e. the SDRAM SmartModel!
According to them, the problem seems to be located in the swift interface.
The same bug was experienced at the Support Center on the V3.4b, and they
issued a STAR (bug 37573).
The bad part of the story is that we have been told this bug will not be
solved until the next releases are available. This means that for our
design we cannot use the VSS V3.4a (now changed to 3.4b) on any of the
stations we have (including the fast Ultrasparc), so we are still simulating
with the V3.3b, waiting more than 3 days to know the simulation results!!
- Pier Garino
CSELT (Centro Studi E Laboratori Telecomunicazioni)
( ESNUG 250 Item 8 ) -------------------------------------------- [9/6/96]
Subject: ( ESNUG 247 #3 248 #3 249 #1) Opinions On Hardware Emulators
> Real gates vs. "emulation gates" -- unlike the comment someone made,
> emulation gates are NOT 2-3X smaller than real ASIC gates -- the actual
> gate capacity depends on the design style -- much like in an ASIC.
> Emulation gate was designed to be a unisex unit of measure which includes
> a certain combination of memory bits and logic gates.
From: Dennis Skey <dskey@ctron.com>
John,
Quickturn uses FPGA's whose capacities far exceed what they market. Xilinx
has limitations which Quickturn is forced to worked with (i.e. compile times,
successful compilation of fpgas,....etc). Thus the compile times and
capacities that Quickturn gives a customers are hard to pin down, but this
should not be the main issue for comparing emulation companies. Quickturn
has so many solutions for the entire industry it is hard not to choose them.
- Dennis Skey
Emulation Consultant
---- ---- ---- ---- ---- ---- ---- ----
> Aptix -- Price leader. U.S. $0.50 (or less) per gate emulation. But
> size limit of ~100 kgates and it's the Radio Shack kit of emulators.
> You get a board, not a box, and you spend a lot time shuffling FPGAs
> in and out of it. You provide your own Tektronix/HP logic analyzer
> for debugging. Fast compiles and simulation times. No DAC parties.
From: michel@aptix.com (Michel Courtoy)
Hi John,
[ Call Me Ishmael ] got a few things right on his survey of emulation
vendors but then he misfired on a few others.
Probably the key misunderstanding is on the issue of open systems versus
black boxes for emulators. Aptix has chosen to offer open systems for its
emulators while all other vendors have opted for a closed environment.
Why do open systems make sense for emulation?
The Aptix patented open architecture makes it possible to incorporate all
system components in the programmable emulation environment -- including
the processor, DSP, memories, I/O interfaces, and FPGAs for the new ASIC.
The user is free to select the latest and greatest FPGA increasing the
capacity of the emulator with the introduction of every new FPGA family.
This combination results in true system-level emulation.
Another key benefit of the Aptix open architecture is the higher
emulation speeds: Aptix users average 20MHz. It means that many emulated
designs can now run in real-time, eliminating the system slow-down
issues. A regression test that would have taken a day to complete with a
traditional emulator only takes one hour with the open architecture Aptix
system making it possible it iterate multiple times on the design in one
day of work.
Finally, the reviewer is right on when it comes to pricing: Aptix is the
leader in that department. Looking beyond the initial acquisition cost,
price is of increasing concern because hardware/software co-design is
needed to develop the 'whole' system. The availability of low-cost
'replicate' copies of the emulator can considerably speed up development
times and increase quality. Aptix is the only vendor to offer an
economically viable replicate option.
Is it just me or is there really a correlation between the prices charged
by the vendors and their DAC parties?
- Michel Courtoy
Aptix Corporation
( ESNUG 250 Item 9 ) -------------------------------------------- [9/6/96]
Subject: (ESNUG 248 #4 249 #4) Problem VHDL Elaboration w/ Multiple Libs
> We've had the same experiences with multiple libs for Version 3.3b and
> 3.4b. The only solution is designs are analyzed with the entity
> and architecture in one (!) analyze call either by putting both in one
> vhdl file or calling dc_shell> analyze ... { entity architecture }
From: Iain Finlay <ifinlay@qualcomm.com>
Hi John, I just wanted to follow up.
The problem I reported a few weeks ago (ESNUG 248 #4) is accurately
described by Victor Preis (249 #4). It occurs when entity and
architecture are in separate files and are analyzed during separate
sessions of the VHDL Compiler. In this situation the elaborate command
fails to bind to components resident in design libraries other than
WORK if they are referenced solely from a context clause (library XX;
use XX.YY.all;) in the architecture's file.
An alternative workaround to analyzing entity and architecture
together is to duplicate the context clause of the architecture in the
entity's file.
I've logged this problem with Synopsys.
- Iain Finlay
Qualcomm
( ESNUG 250 Item 10 ) -------------------------------------------- [9/6/96]
From: che.wong@tempe.vlsi.com (Che Wong)
Subject: Electrical Problems From Using The "Translate" Command
Hi, John,
I was wondering if you have any experience with the translate command. I
have tried to use it on a gate-level design to convert from one standard
cell library to another and I am running into a slight snag. From the small
test cases I have run, the logical function of the final design appears to
match the original design. However, the electrical characteristics do not
match. The new design uses many minimal output drive gates in place of the
higher output drive gates of the original design. I have tried to use the
derive_timing_constraints command before using translate, but the drive
substitution still occurs. After the translate, I have tried to run an
incremental_mapping on the design, but not all of the minimal drive cells
got upgraded.
Is this a limitation of the tool (I am using 3.3b), a cell library
problem, operator error or something else?
The designs I need to convert to the new library implementations are OLD
designs. We have very little documentation on them, so it is difficult to
create meaningful constraints for the designs outside of the clocks. We are
bringing the designs over to the SYNOPSYS enviroment through EDIF format
files. I don't really want to set a dont_touch attribute on the minimal
drive gates because they are used in parts of the original design. Ideas?
- Che Wong
VLSI Technology
( ESNUG 250 Networking Section ) -------------------------------- [9/6/96]
Austin, TX -- Brooktree seeks ASIC engineers w/ Synopsys & Verilog exper.
for multimedia designs. Death to headhunters! "mulligan@brooktree.com"
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