Top Ten Ways of Knowing You're Working with the Wrong EDA Vendor
10. Salesman thinks "logic synthesis" is an obscure philosophical concept
invented by Aristotle.
9. Software runs only on PCs with flawed Pentiums.
8. Customer support hotline turns out to be 1-900 number that charges $3
per minute to talk to a young woman named "Pebbles."
7. Company has just invented an HDL that requires all submodules to be
written as haikus.
6. When you call to complain about not having enough ASIC libraries,
customer service rep suggests you go downtown and use the main
library instead.
5. Entire two-week training session consists of instructions on how to
boot the application.
4. Vendor charges 12 percent per year maintenance just to fix bugs that
shouldn't be in the product in the first place.
3. FAE tries to demonstrate prodouct on a typewriter.
2. Vendor offers to outsource your entire CAD department by e-mail.
1. Vendor was just mistakenly acquired by a large farm implement company
who thought EDA stood for "equipment developed for agriculture."
I'm shamelessly pinching this from Richard Goering (an EE Times editor)
who used it as a panel ice breaker at PLD Con/WinEDA '95.
- John Cooley
the ESNUG guy
( ESNUG 220 Item 1 ) ---------------------------------------------- [7/7/95]
From: linjeff@tk0.taisel.alcatel.com.tw (Jeff Lin)
Subject: Weird Asynch Pins In Xilinx VSS Library
Dear John,
I found it odd that there are 2 asynchronous pins each: GSR & CLR for cell
FDCE, GSR & PRE for cell FDPE in the Xilinx xc4000_FTGS.vhd of XACT5.1 for
simulation of VSS. Has anyone found problems with these cells?
- Jeffrey Lin
Alcatel
( ESNUG 220 Item 2 ) ---------------------------------------------- [7/7/95]
From: monroe@ctron.com (Donald Monroe)
Subject: Raising A DesignWare Module Through Hierarchy
John,
Is there a way to move a module that is N levels deep in the hierarchy up to
the top level and have Synopsys create the appropriate port lists through all
the intermediate levels? We are having a particular problem with the PCI
DesignWare, where the I/O module is instantiated by DesignWare which is
instantiated by our application module which is instantiated by the top level.
The I/O module would really like to be at the top level. Any suggestions?
- Don Monroe
Cabletron Systems
( ESNUG 220 Item 3 ) ---------------------------------------------- [7/7/95]
Subject: (ESNUG 217 #5) How To Handle Timing Through Bidirectional Ports?
>How do other people handle timing through bidirection I/O's -- especially
>to/from an external RAM? I have a whole load of bogus loop paths through
>bidi's (I don't generate write data and clock it back in!). disable_timing
>only works to disable paths WITHIN cells, not between cells. set_false_path
>only works on path endpoints, so I can't just disable the piece of wire
>connecting the input pad's input to the output pad's output. SolvIt
>recommended doing set_input_delay and set_output_delay on the pins of the
>cells involved. This works, but it has a nasty side effect....
From: [ The Synopsys Support Center ]
John,
This is in regards to the issue of whether or not Synopsys tools can time
through pads to external RAMs. Several people within the company discussed
this, and we have two reasonable ideas on how to do this. No one has known
anyone who has attempted to time external RAMs using the Synopsys timing
analyzer. This does not mean no one has, but this may be the first to do it.
1) Use set_max_delay, with the -from and -to options specifying the
input_pad's input (or output) pin to the output pad's output(or input)
pin. The value of the delay constraint should be very large, to make
sure that the tool would not have any trouble seeing the path as meeting
constraints, no matter what. The advantage of this method is that it
is fast and easy. Set_max_delay is meant to constrain combinational
(not sequential) paths, so the -from and -to can specify most pins, not
just valid start points and end points. This also avoids any side
effects with clocks. The disadvantage is that the tool still thinks the
path is there, but as long as it meets constraints by a wide margin,
the tool will ignore it for timing and compilation.
2) Build your own Synopsys library component for the RAM, and time the chip
as a core block with the RAM next to it. This is what you suggested
originally. You don't need an LC license to build new cells with timing,
LC is only needed to describe functionality. This method would be much
more time-consuming, but its advantage is that any false path is
completely broken by the set_input_delay and set_output_delay commands
that are used as specified in the solvit article. The tool does not see
that path as existing. The effect on the tool is no different than
method 1, but some would call this the cleaner solution, because the
paths are gone, instead of being masked by a large set_max_delay.
In general, the set_max_delay would be easier for most bidir timing problems,
so we will put this into a solvit article, with a reference to the original
article that suggested breaking the timing paths.
- [ The Synopsys Support Center ]
( ESNUG 220 Item 4 ) ---------------------------------------------- [7/7/95]
Subject: (ESNUG 214 #5 215 #5 217 #4) Specific Reasons Why Synopsys Sucks!
Michael M.Y. Hui wrote:
>It is not difficult for a logic designer to learn how to write high quality
>synthesizable code. But it is very hard for even a computer science M.Sc.
>w/ ample E.E. CAD tool exposure to learn how to use Design Compiler
>properly! The fault is in the inflexable design database, unclear commands,
>apparently random (Bill Gates' famous phrase) naming of options &
>attributes, overly complex component library system, and of course, bugs
>galore. However, let's not bite the hand too harshly that feeds some of us.
> 1. Synopsys has large market share.
> 2. Design Compiler is very hard to use.
> 3. Synopsys Gurus are rare, and they command high salary.
From: bodack@sican.de (Ruediger Bodack)
I do agree to the first point, also to the second, but I think this is a
result of a complicated topic. Compared to schematic entry it is real
fun to learn several compiler instructions. I don't think, there are to
many unclear commands. There are just a lot of them, but only to meet
everybody's different problems. At our company young guys use Design
Compiler after 4 weeks learning it. I'd like to add:
4. Synopsys has a very efficient online help.
5. The hotline in Germany is really helpful.
6. Synopsys has a lot of software bugs but is has a very short
feedback in correcting them. Have you ever reported a bug in your
MSWindows-system and have you seen the correction of it in the next
version?
7. Synopsys has a very good combination of command-line and graphical
user interface. Theres no large framework that does obscure things
in thousands of files and windows.
But, if all tools of Synopsys are going to look like the Windows stuff, like
the Library Compiler, I'll cancel my job and become a farmer.
- Ruediger Bodack
SICAN GmbH, Germany
---- ---- ---- ---- ---- ----
From: greg@cqt.com (Greg Bell)
Concerning the randon naming, I couldn't disagree more. I can't tell you how
many times I've guessed at the name of a variable or command and gotten it
right because of naming consistency. The variable auto_link_disable tells me
exactly what it does. It *could* have been named al_disabl.
Not only that, but the *extensive* help almost never leaves you stranded.
How many tools allow you to do things like 'help HDL-103' to get an extended
description of why its unhappy along with instructions for what to try next?
In fact, just as a test, I just tried to read in a non-existent file:
design_combobulator>read -f vhdl none.vhd
Error: Cannot read file 'none.vhd'. (UID-58)
{}
Now, just in case that's not enough information, I could do:
design_combobulator>help UID-58
Command Reference N. Messages messages
NAME
UID-58 (error) Cannot read file '%s'.
DESCRIPTION
This error is generated when you try to read a file
which is protected or does not exist.
WHAT NEXT
Check and correct search_path, then reinvoke the read command.
V3.2 Synopsys Inc. 1988-1995. All rights reserved. n-1
Now c'mon! How much more friendly can you GET? Most of what I know about
Design Compiler I learned through the help, and the rest I learned from
the on-line manuals (the *complete* set is online, along with a master
index, and a full text query search feature). Everyone here thinks I'm
the local Synopsys guru because I can come fix it when they have a problem,
but the first thing I always type is 'help <ERROR ID>' and just read!
Add to that the flexibility in syntax like:
find (port, "*") or find port, "*" or find port "*"
Now I will side with you about the bugs. I wish software companies would
concentrate on quality instead of packing more and more features (past a
certain point). Right now, Synopsys is very functional, feature-wise, and
it would be great if they would release a version whose selling point was
"It's rock solid!". That's not what sells products, so its partly the
consumer's fault. Its the same reason some popular Windows based apps keep
getting fatter and slower and more buggy... features sell and get magazine
write-ups, quality (ie. lack of bugs) is harder to recognize, almost
impossible to quantify, and not as "sexy" as things like ChartWizards.
Concerning Design Compiler being hard to use, I say: Not necessarily. You
can do basic synthesis quite easily. Read file in, include a simple baseline
constraints file, compile, save file out. I've seen engineers up and running
in a half hour. I complain about crappy software as much as the next guy,
and I've never been one to kiss butt when a product sucks, but Design
Compiler, with its imperfections, doesn't fall into that category.
- Greg Bell
CommQuest Technologies, Inc.
( ESNUG 220 Item 5 ) ---------------------------------------------- [7/7/95]
From: sgolson@trilobyte.com (Steve Golson)
Subject: Design Size Dependant Hierarchical Timing Bug (3.1b & 3.2b)
John,
I have timing report from a design, showing a 44.12ns path. I move up a
level in the hierarchy, so the previous design is now an instance named
"cntl" in this upper design. Now the *same* path now shows 214.02ns delay!
*All* of the incremental delays have increased. This has the same wireloads,
the same operating conditions, report_net shows the same loads & resistances
on the nets... what the heck is going on?
The first incremental delay has some increase due to the loading on the
input port, but why have the *internal* delays changed? Somehow the delay
calculations seem to be affected by the size of the design, but I can't
figure out how. (Kurt Baty has seen this as well, and logged it with
Synopsys.)
This happens in 3.1b and 3.2b. I will try 3.3a real soon now.
It appears that this bug *only* occurs if you have a non-default driver on
your input ports (i.e., if you leave it with the default "infinite" drivers,
everything works). It doesn't matter if the path uses the clock or not. It
doesn't matter if you have defined the clock or not. If you put a drive on
your clock, things start to break. They break in different ways depending
on where in the hierarchy you are looking at the path.
- Steve Golson
Trilobyte Systems
( ESNUG 220 Item 6 ) ---------------------------------------------- [7/7/95]
From: [ "an anonymous FPGA Compiler user" ]
Subject: Synthesizing FPGA w/ v3.3a Crashes While In v3.2 Everything's OK
John, for intra-company political reasons please have me be "an anonymous
FPGA Compiler user"; I don't want to get in trouble for this.
A number of engineers at my company have been getting crashes of Design
Compiler v3.3a with designs that ran just fine in v3.2. Usually the core
dump occurs in elaboration or in high level opto (before any FPGA tech
mapping). Have any other users reported instability in the production
v3.3a code compared to v3.2? Is the new version "fussier" about compiling
even if the code has warnings (not errors, but just warnings) during the
read or analyze/elaborate step? Any feedback would be great!
- [ "an anonymous FPGA Compiler user" ]
[ Editor's Note: I've also heard grumblings that v3.3a has been fatal city
for the non-FPGA (i.e. ASIC design) crowd using Design Compiler. - John ]
( ESNUG 220 Item 7 ) ---------------------------------------------- [7/7/95]
From: Jim.Avant@Sciatl.COM
Subject: What's The Real Scoop On Synopsys & Solaris 2 ?
John,
Synopsys documentation claims that Synopsys should run fine on Solaris 2.
Does anyone know different? Also what about Cadence, IKOS, Motive, etc?
The reason I ask is that instead of purchasing a bunch more Sparc 20s for
the new guys we're hiring for ASIC & FPGA development, I'd like to buy a
couple of 4 processor boxes from Sun and connect through X-Windows Server
S/W from our PCs. However, this is only viable using Solaris 2.
- Jim Avant
Scientific-Atlanta
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