( Post 126 Item 1 ) --------------------------------------------------------
From: trevor@ncd.com (Trevor Pearman)
Subject: Random number generator
Does anybody have a good random number generator for vhdl? We are having
problems getting good random numbers from the Synopsys supplied package. Its
period is too short.
Ideally, we would like an equivalent to the Berkeley random function.
Alternatively we would like to simply call this random function from VHDL.
-- Trevor
-- -- -- -- -- --
Editor's Note: I've had a recent flurry of these requests so I'm
reposting ESNUG 81 Item 1 to fill the need. - John
-- -- -- -- -- --
From: markg@ichips.intel.com (Mark Gonzales)
Subject: (Repost ESNUG 81 Item 1) "A Better VHDL Random Number Generator"
Not, strictly speaking, a bug, but the random number generator
(procedure random) in the synopsys distributions.vhd package has a cycle
length of only 8k numbers, making it rather useless. We think this is a
better one (disclaimer: use at your own risk):
procedure RANDOM (variable Seed: inout integer; variable X: out real) is
----------------------------------------------------------------------
-- Random Number generator from:
-- The Art of Computer Systems Performance Analysis, R.Jain 1991 (p443)
-- x(n) := 7^5x(n-1) mod (2^31 - 1)
-- This has period 2^31 - 2, and it works with odd or even seeds
-- This code does not overflow for 32 bit integers.
----------------------------------------------------------------------
constant a : integer := 16807; -- multiplier 7**5
constant m : integer := 2147483647;-- modulus 2**31 - 1
constant q : integer := 127773; -- m DIV a
constant r : integer := 2836; -- m MOD a
constant m_real : real := real(M);
variable seed_div_q : integer;
variable seed_mod_q : integer;
variable new_seed : integer;
begin
seed_div_q := seed / q; -- truncating integer division
seed_mod_q := seed MOD q; -- modulus
new_seed := a * seed_mod_q - r * seed_div_q;
if (new_seed > 0) then
seed := new_seed;
else
seed := new_seed + m;
end if;
X := real(seed) / m_real;
end RANDOM;
- Mark Gonzales markg@ichips.intel.com
Not speaking for: Intel Corp. (503) 696 4551
( Post 126 Item 2 ) --------------------------------------------------------
From: curtis@devnull.mpd.tandem.com (Curtis Jones)
Subject: 3.0 replace_synthetic warning
Beware of the replace_synthetic command. The following should be the
default (if you check any command.log file, you can verify this)
hdlin_replace_synthetic = "FALSE"
We were using the following in our scripts
"replace_synthetic -ungroup"
after link and before compile. The reason was that we wanted to strip off
the hierarchy which is created when Synopsys uses an element of the synthetic
library (i.e. adder, incrementer, comparator), but we didn't want to
ungroup the entire design. We were also concerned that Synopsys would
select synthetic elements and then not optimize them. As shown in the
example below, these concerns were not justified.
The warning about replace_synthetic is that if certain library
elements are selected, then your clock constraint is REMOVED!!!
The error seems to be related to the use of certain synthetic elements.
The specific case which failed was in using the incdec element (an
incrementer/decrementer). Our code uses 2-bit, 3-bit, and 7-bit updown
counters. We got these warnings when using replace_synthetic:
"Warning: Design 'MODULE' inherited license information from design
'DW01_incdec_width2'. (DDB-74)
Warning: Design 'MODULE' is being converted to a limited design. (DDB-75)"
later, we saw this:
"Warning: The following endpoints are not constrained for maximum delay."
[ Followed by a list of ALL flops in the module !!! ]
If we did report_clocks, we saw:
"No clocks in the design"
Example Verilog Code fragment which failed:
reg [1:0] Pointer_2bit;
wire Reset_L;
wire Push;
wire Pull;
always@ (posedge Clk) begin
if (!Reset_L) begin
Pointer_2bit = #1 2'b00;
end
else if (Push && !Pull) begin
Pointer_2bit = #1 Pointer_2bit + 1'b1;
end
else if (!Push && Pull) begin
Pointer_2bit = #1 Pointer_2bit - 1'b1;
end
else begin
Pointer_2bit = #1 Pointer_2bit;
end
end // always
We could not find a way to write the code to avoid this problem. This
included moving the elseifs/else to a separate always block. So we removed
the replace_synthetic command, and took a closer look at the generated gates.
(Interestingly, the 2-bit and 3-bit incrementer/decrementer code fragments
were inplemented using simple gates; no synthetic elements were selected.
It did build a 7-bit incrementer/decrementer, and it's apparently a good
implementation.)
The following example shows the result of NOT using replace_synthetic
on a different code fragment:
reg [3:0] comp_val
reg comp_val_gt0
assign comp_val_gt0 = (comp_val > 4'b0000) ? 1'b1 : 1'b0;
A "simple" representation of the above is a 4-input OR gate.
Synopsys 3.0 selects a DW01_cmp2_width4 element from the synthetic library,
& hooks it up as follows: (see DesignWare Databook for function's data sheet)
MODULE_DW01_cmp2_width4_0 r0 ( .A({1'b0, 1'b0, 1'b0, 1'b0}),
.B(comp_val), .LEQ(1'b0), TC(1'b0), GE_GT(comp_val_gt0) );
and when it instantiates the above cell, it optimizes it down
to a 4-input OR.
module MODULE_DW01_cmp2_width4_0 (A, B, LEQ, TC, LT_LE, GE_GT);
input [3:0] A;
input [3:0] B;
input LEQ, TC;
output LT_LE, GE_GT;
or04d1 U1 (.a1(B[3]), .a2(B[2]), .a3(B[1]), .a4(B[0], .z(GE_GT));
endmodule
- Curtis Jones
Tandem
( Post 126 Item 3 ) --------------------------------------------------------
From: Steve DeGroof <steve@sun1.atitech.ca>
Subject: 2.2b 'write_script' Crash
I've been having trouble with the 'write_script' command. If I 'characterize'
a block that has more than one unconnected input, and do a 'write_script' for
that block, Synopsys crashes. (this is v2.2b)
Anyone else run across this problem?
- SD
-- -- -- -- -- -- --
From: jcooley@world.std.com (John Cooley)
Yes, Steve, I've seen that one myself. What's going on is that Synopsys
sees the unconnected outputs as equivalents and seems to dislike this
a lot. If you look at the file written out by the write_script, it died
immediately after writing something like "set_equal port_one port_two"
where port_one and port_two are the unconnected ports.
This also happens if you try to a write_script on a module with two or more
constant inputs (like having them all tied to logic high) or designs with two
or more unconnected inputs (because they all default to the same logic value.)
How to get around this? Connect these ports to something OR remove them
from your module port list altogether. (Sorry, these are the only solutions
that have come up after lots of research by me and Synopsys.)
I'm not sure if 3.0a has this problem or not.
-John Cooley
ESNUG Moderator
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