( Post 89 Item 1 ) --------------------------------------------------

From: Bob Warren <warrenb@inmos.co.uk>
Subject: ESNUG Outputs not used for internal feedback.

John,

Have you ever had a design where some of the outputs are also used 
as inputs within the design, viz:

              /------\
       [>=====|logic |         |\
              |      |---|>o---| >o---+---[>
          +---|      |         |/     |
          |   |      |                |
          |   \------/                |
          |                           |
          +---------------------------+

Q: What happens when the load on the output is not quite what you 
   expected?

A: The timing analysis of the innards of the block gets messed up!
   (Could be a max_path or a min_path problem).

In order to "isolate" the timing analysis of the "innards" of a 
particular block from the effects of any output loading, the 
"feedback" must be taken not from the actual output, but from some 
earlier point in the path, even if this means adding an extra 
gate, viz:

              /------\
       [>=====|logic |         |\
              |      |---|>o-+-| >o-------[>
          +---|      |       | |/
          |   |      |       |
          |   \------/       +-|>o----+
          |                           |
          +---------------------------+

Q: What is the mechanism for persuading the Design Compiler to 
   do this?

A: Assuming that you are using a CMOS design, and that timing is 
   constrained by "max_transition" and "max_fanout" is redundant 
   (which is the norm); use max_fanout in the following manner:

set_max_fanout          100                     find(design,"*")
set_fanout_load         100                     all_outputs()


Bob Warren, Inmos Ltd., Bristol, UK.