( SNUG 99 Item 35 ) ----------------------------------------------- [3/31/99]

 TRAPPED IN YUGOSLAVIA  There are two Synopsys product lines that are
 trapped in ugly EDA war zones with lots of unfriendly 'questionable'
 characters surrounding them.  FPGA Express is trapped in a world where
 it's fighting Synplicity and Exemplar for the 'high end' of an FPGA
 market that's flooded with free (or virtually free) synthesis tools
 from Xilinx and Altera.  Synopsys VSS is trapped fighting Cadence
 Leapfrog and a cheaper Model Tech for the 'high end' of an ever
 cheapening VHDL sim market.  (It's constantly being undermined by
 the super-cheap/free VHDL simulators from Aldec, or ViewLogic, or the
 $99 Cypress Warp.)  You can't make a hell of a lot of money selling
 cows when everyone is giving milk away for free.

   "Right now we've got over 100,000 design sites (MaxPlusII & Quartus)
    with customers.  On a rough order of magnitude, Xilinx has a simular
    number of seats.  Fifty percent of our seats are 'free' and the other
    fifty percent are 'purchased' seats.  The 'free' versions only support
    our proprietary Altera-HDL (A-HDL).  Of the 50,000 'purchased' seats
    about 15,000 of them support VHDL or Verilog.  (All have A-HDL.)  To
    be honest, I couldn't tell you the exact split between VHDL or Verilog
    with any certainty, because we really don't care, and support both
    equally.  However, qualitatively, I'd say 10,000 (10% overall) are
    VHDL vs. 5,000 (5% overall) are Verilog."

       - Robert Beachler, Sr. Director of Development Tools, Altera