( SNUG 99 Item 13 ) ----------------------------------------------- [3/31/99]
SEWARD'S FOLLY (PART DEUX?): In 1867, the U.S. Secretary of State, William
Seward bought Alaska from the Russians for $7 million. At the time, this
purchase was called "Seward's Folly" because it was popularly felt that
the U.S. would never get $7 million worth of return out of Alaska. (In a
sense, public opinion at the time was right, because it's estimated that
it took about 35 years to recoup $7 million of surplus taxes from the
Alaska economy.) The Synopsys equivalent of this came when they bought
System Science (VERA) for $26 million. It's well known that verification
and functional testbench generation is something that we engineers drool
at because we *hate* creating testbenches, so the need is there for VERA
and Specman. (Specman is a competing functional testbench generation tool
from Verisity.) Functional verification (sim done in Verilog or VHDL) is
supposedly taking over 50 percent of design efforts these days. If you go
to DejaNews, you'll find there are around 5,300 posts every year on either
Verilog or VHDL. And it's growing. Yet you'll only find 6 VERA posts and
2 Specman posts in DejaNews, and only 7 posts on each if you grep an ESNUG
archive! Yes, Synopsys recently announced VeraCore (VERA being used with
IP) and, yes, it's integrating VERA with the Eagle HW/SW co-simulator,
but if VERA is an up-and-coming widely used tool, shouldn't there be more
posts from users on it? Is Synopsys going to have to wait 35 years to
recoup its VERA investment?
"VERA - Mehdi Mohtashem (mr VERA). Most stuff in files. Sales pitch
that was very technical and example laden.
- Can reuse existing verilog or C. Can call routines/tasks inVERA
- Interfaces to simulator via PLI . Going direct with VCS to speed
it up.
- Can handle re-entrant calls without multiple instantiation. Fully
recursive via virtual ports. Can call multiple times at anytime.
- Cyclebasedwith event driven options
- random and directed random constructs to produce stimulus
- Self checking with floating expects.
- User defined functional coverages (not line code coverage) of
stuff like fsms. Gives reports. Can react to coverage and
dynamically redirect sim on the fly.
- 2 to 10x reduction in overal verification: Speeds up verification
development, verification debug, and result review(regression).
IP released with VERAcore gives verification test suite that can run
without VERA license."
- Peet James of Qualis Design
"Whenever I teach Verilog and Verilog synthesis classes, I always
take a short poll. The question: 'How many engineers in this room
prefer writing testbenches over doing ASIC design work?' Of more
than 600 engineers taught in the last two years, fewer than five
preferred writing testbenches."
- Cliff Cummings of Sunburst Design
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