( SNUG 10 Item 11 ) --------------------------------------------- [04/15/10]
Subject: What 238 users think of the CoWare and VaST acquisitions
MORE APATHY: Look below at the user stats and it's obvious that the
majority of SNPS users still have very little interest in C-based design
or modelling. What's worst is many of those few who DID care do NOT want
to pay for C models -- they'd rather get them free or mostly free in a
Synopsys package deal -- not a good ROI for a rumored $80 to $90 million
CoWare acquisition. Ouch.
Synopsys recently acquired CoWare and VaST, along with Virtio some
3 years earlier. As a Synopsys customer (choose ALL that applies):
0- Our group does not do C stuff.
: ########################################################### 59%
1a- Despite Aart's interest, C is experimental EDA at best.
: ######################## 24%
1b- It's the future; we're glad Aart bought them.
: ######## 8%
2- Oh, no! It gives SNPS a near monopoly in SystemC models!
: ##### 5%
3a- Cool! It's free SystemC models in our SNPS package deal!
: ####### 7%
3b- Cool! We'd even pay good cash for the SystemC models!
: # 1%
4- Don't care. We like (name co's) C tools more instead.
Forte Cynthesizer : ## 2%
Mentor CatapultC : ## 2%
Synfora Pico : 0%
Cadence C-to-Silicon : 0%
AutoESL : 0%
Comments?
---- ---- ---- ---- ---- ---- ----
We don't care about SystemC; we like System Verilog's DPI more. :)
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
'C' based stuff does nothing to improve productivity and in many cases
makes it worse. It appears to be applicable only to those individual
that were experts to begin with. But the TAM for fancy tools to make
'experts' more productive is very small.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
C design is too new.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
Glad Aart bought them. Commercially it might be difficult in the long
run. But what is easy?
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
System Verilog Rules!!!
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We do not do a lot of C stuff, a few engineers do a little.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We have just started to evaluate the C approach. Our test case is
using CatapultC.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
I'm trying to convince management to look at C synthesis, to me it's
just a matter of time before RTL goes the same way as logic design by
schematic capture or logic design directly in layout.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We had a lot of SystemC activities in the consumer division in the
past. Currently we don't really use SystemC for design.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
VaST/SNPS was the strongly preferred. SNPS models have huge problems
running in a VaST environment. So its good if they now work more
closely together. (It cannot get worse!).
Good (accurate, high speed) SystemC models are not available for free
and for sure someone has to pay for them. We're glad to pay if we get
really fast models. Now it's a business issue - hide the cost in the
RTL license, extra lic for SystemC, one time fee?
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We use the free Veripool Verilator to convert Verilog RTL into C++ models
for cycle accurate validation.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
Torn between "experimental" and "it's the future".
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
Our group has been surveying SystemC simulation platforms for the last
two years. The space was too fragmented. Glad it's cleaned up.
This is also good news for remaining competitors that have invested in
SystemC and TLM-2. They can position themselves as the "other" solution.
Also I don't want to pay a single cent for SystemC models. They need to
be ready when I dream up my next chip. It can take several man-months
for an important piece of SystemC IP to mature. That's eons in terms of
system simulation time.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
Interested to see what comes out of this acquisition. Will it be based
on standards (eg SPIRIT, ...) or mix of SNPS+CWR+VAST? Not so many
alternatives on the market. It will probably reinforce internal
development. And still weak around TLM / RTL cosimulation / coemulation
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
As an old Synopsoid, I know that Aart just loves collecting companies.
Like others stamps. Often doesn't have an impact on product portfolio.
And the staff numbers of SNPS are the same after 1 year, at latest.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
It's about time EDA companies are getting serious about SystemC.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We like (INTERNAL) C tools more instead.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
The big question is where is C synthesis to compete with Mentor
CatapultC or Cadence C2S ???
Rumor: C-to-RTL equivalence checking is coming out, at least this time
its formal equivalence first.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We do system-level design and for sure something with C. I currently
just don't know what my colleagues are up to.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We currently use System C for high level data path modeling but NOT for
design. Speculatively on the design side, I believe it may be useful
for modules where verifying the algorithm is more important than the
implementation, and perhaps where data transforms are already done
typically in SW. I do not believe that doing an entire design in
SystemC will improve verification performance once the design has enough
state timing information to be useful to verification.
- [ An Anon EDA User ]
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