( SNUG 10 Item 6 ) ---------------------------------------------- [04/15/10]
Subject: What 238 users think of Design Compiler
APATHY RULES (Part I): Sure, it's not the days where Synopsys owned 90%+
RTL synthesis market share, but with 76% of DC users happy with DC, don't
look for a lot of turnover here. Cadence RTL Compiler is the biggest
"threat" to DC, followed by Magma Talus Design and newbie Oasys RealTime
(see ESNUG 484 #2) -- yet combined they're less than 24% of the space.
With regards to Design Compiler, DC-Topo, DC-Ultra, etc., does
your group plan to (choose what applies to your situation):
1- We're sticking with DC, it's the best price.
: ################################## 34%
2- We're sticking with DC, it's the best technology.
: ########################################## 42%
3- We're considering (name tools) to replace DC.
Cadence RTL Compiler : ##### 5%
Magma Talus Design : #### 4%
Oasys RealTime : ### 3%
4- We've already switched to (name tool).
Cadence RTL Compiler : ######### 9%
Magma Talus Design : #### 4%
Comments?
---- ---- ---- ---- ---- ---- ----
Out of inertia, and considering the state of the art in low power
synthesis (power gating, UPF support, stuff that DC is gettting
better at in the latest releases), we'll stick with DC.
Plus migrating to another tool means making sure that everything we
need for synthesis/scan insertion works (or mostly works and the bugs
are easily work-aroundable).
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
Haven't done serious evals of competition.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
Haven't looked at competitors in last several years.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We have tried Magma as well, but only for about 1.5 years. Switching
was not very comfortable, but what annoyed us were incompatibilities
when changing tool versions (constraints); also M-tcl different to tcl.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We're sticking with DC because it's the standard (for now) and we have
to do what is standard to minimize risk -- we'll be at least kicking the
tires on Oasys DA, but we're not in their sweet spot of size.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We're actually sticking with DC because it's internally available,
and we have a lot invested in the flow we have built around it.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
Magma Talus Design.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
Cadence RTL Compiler.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
3- We're considering RTL compiler to replace DC.
Not "considering", but "forced to use in future". This stuff is rock
bottom. If we COULD have chosen, it would have been at least DC Topo.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
Have Oasys
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We'll stick with dc-shell because it is good enough and we've invested
a lot of effort in it over the years. A few percent of improvement
here or there with another tool is not enough to justify bringing in a
new tool.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
Certainly not the best price, but still a lot of value for the price.
Other tools can be good, too. But DC seems to make a kind of standard.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
I'd like to look at Oasys in the future, maybe even RTL-Compiler from
Cadence since its part of our SOC Encounter license.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
DC-Topo integrates well with ICC which is what we use for PnR.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We have been using Cadence RTL compiler for past few years.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
Package deal!
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We've already switched to DC-Graphical and Cadence RC Physical.
DC-G not saving the DEF of the placement is really dumb.
RC-Physical seems to be gaining ground, placement correlates
well with Encounter, but having a placement not scan-inserted
is not good either.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
Considering RTL compiler
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We're sticking with DC (Ultra) because DC-TOPO brings not much to the
table in terms of QoR given its setup headache and thirst for "tapeout
worthy data" when you don't have any (yet).
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
DC is the "standard" and as an IP company it is very important for
us to be DC compatible.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We're sticking with DC because it's a proven process, and most new
designs are being implemented in FPGA, not ASIC.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
Using DC not so much price, but part of IBM's flow.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We're sticking with DC, it's already in the budget & we haven't reviewed
any new tools this year.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
Sticking with DC because we use Synopsys backend tools
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
Can't change. Not sure if DC is the "best" technology, but we have
too many scripts and flow based on DC.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We are planning to move to Encounter as a replacement to DC, but
DC is costly.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
Cadence RTL Compiler. Thing is, we used to use DC for synthesis and
Conformal LEC for formal verification, but that stopped working pretty
much with DC Ultra -- which makes optimisations that Conformal LEC can't
follow. I've switched to RTL Compiler and so far I'm content. Not
enthusiastic, but satisfied.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
So many engineers are familiar with DC, and it's very difficult to
switch to other tools.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We are just evaluating Synopsys for our first ASIC. We primarily use
Synplify for lots of FPGA stuff.
- [ An Anon EDA User ]
---- ---- ---- ---- ---- ---- ----
We have a full Cadence flow and enjoy the situation to NOT discuss which
behaviour is bug or feature - it's all Cadence issue.
- [ An Anon EDA User ]
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