( SNUG 05 Item 9 ) ----------------------------------------------- [12/20/05]
Subject: Design Compiler vs. Cadence Get2chip/Ambit vs. Magma Blast Create
A NEW INSURGENCY -- Although it's not exactly an apples-to-apples comparison
because Dataquest tracks sales dollars while I track actual license useage,
there's been a small but noticable change in the RTL synthesis market. Note
the Dataquest 2002 numbers:
Dataquest FY 2002 RTL Synthesis Market (in $ Millions)
Synopsys DC ###################################### $132.7 (90%)
Cadence Ambit ### $8.8 (6%)
Synplify ASIC # $2.9 (2%)
Get2chip # $2.9 (2%)
Compare this to now, 3 years later, the 2005 usage numbers:
"In your opinion, how does Design Compiler rank against its rivals
Cadence Get2chip, Ambit, Synplicity ASIC, Magma Blast Create,
Incentia in your eyes? Which synthesis are you using now?"
Synopsys DC ################################### 82%
Cadence Ambit # 3%
Synplify ASIC ## 6%
Cadence Get2chip ######### 21%
Magma Blast Create ##### 11%
Incentia . 1%
While Design Compiler still easily dominates at 82%, Cadence Get2chip 21%
and Magma Blast Create 11% are now on the map as viable, albeit weak, rivals.
What sucks for Synopsys is that there now are working rivals. This means
users can use their existence as a barganing chip. What sucks for the rivals
is that most "insurgent" users use Get2chip or Blast Create *in conjunction*
with DC. They're mostly only fair weather rebels. The moment something goes
wrong, they immediately jump back into the safe, secure arms of Momma DC.
The other thing is that those XG improvements in DC seem to be making trouble
for Get2chip and Blast Create. But for the record, while it's not yet true
for Blast Create, I am seeing a few Get2chip users who have gone "all in";
that is, they completely dumped their DC licenses for Get2chip ones with no
going back to DC. This is new.
Either way, the users win because now there's competition in RTL synthesis.
The only place where Synopsys has lost total dominance in synthesis is in
the specialty Structured ASIC market; 11% of users are designing Structured
ASICs and Synplify ASIC has 6% -- which means DC only gets the leftover 5%.
Not much of a loss because its such a tiny market, but a loss nonetheless.
It's interesting how things have changed in 3 years. My congrats to the
Cadence Get2chip, Magma Blast Create, and Synplicity ASIC teams.
---- ---- ---- ---- ---- ---- ----
Very good, DC-XG, can synthesize a 4 MG design flat in less than 6 hours.
We use DC-XG and Get2Chip. Get2Chip is also quite fast but has too many
loose ends making it unusable for a real tape-out.
- [ An Anon Engineer ]
Currently using DC. Probably moving to XG-mode for next time. Have had a
small chance to play w/ Get2chip and did like what I saw at the time.
- [ An Anon Engineer ]
Design Compiler is working well for us.
- Wanhao Li of Zoran
While the 2004.12 DC variants were behind, apparently most of the ground
has been recovered with the 2005.09 DC-XG version: number of instances is
now on a par with RTL Compiler, QoR (timing) has been improved (still
behind depending on test case). While I have never been impressed with
Get2chip's runtime (similar to DC 2004.12), DC 2005.09 is about 2x faster,
and could be even better if it weren't for some XG idiosyncrasies.
Unlike Synopsys's claim, memory usage has not improved much (say, 10%) and
is still 4x Get2chip's requirement.
After 1 or 2 -SP interim releases, DC 2005.09 will again be a solid
contender. At this point, there are still some bugs that rank right in
the "I can't believe they let that one slip", though (nothing that
crashes, but a human must work around the issue).
We're using DC at the moment and I don't foresee a switch. Rewriting
scripts, translating constraints, checking all that would be too much
work for what our schedule allows. Better stick with the evil we know
and work around issues as they arise than overhaul the synthesis flow.
- [ An Anon Engineer ]
Rate DC very highly, although we have experienced quite a number of
problems moving to XG mode, most notably problems with collections.
It does what it says on the tin.
We initially used Magma for our VHDL synthesis as we were using it for
the place and route, unfortunately we found it had so many problems
we dumped it completely in favour of Synopsys.
- [ An Anon Engineer ]
We use Design Compiler. We did a long evaluation of Cadence Get2chip
late last year. At the time Get2chip gave better results than DC under
identical constraints. But Synopsys AEs and DC XG mode were able to
give us similar results so we stuck with DC.
- [ An Anon Engineer ]
Compared to Get2chip, DC seems to have a lower capacity in terms of
design size, but XG mode has made this much better.
In the process of evaluating Blast Create now to see if Magma knows
something about an RTL-> placed gates flow that Synopsys doesn't.
Currently using mostly DC.
- [ An Anon Engineer ]
Magma Blast Create seemed to be decent but definitely not up to par with
DC or Get2chip in either results or features. If they keep working on it,
it could get there though as it seemed to have potential. I have not
looked at the Magma releases of the last 6 months however. Last I looked
at Synplicity ASIC (near 2 yrs ago) it was really not even a reasonable
contender due to features, capacity, etc... Maybe it's improved but it
did not impress me as a serious ASIC synthesis tool back then so we have
not considered it since.
DC was falling pretty far behind Get2chip until just recently. It was
falling behind to the point of becoming irrelevant. The 2005.09 DC
release seems to be a major step forward. I'm finding Get2chip still
besting it in some cases but DC now bests Get2chip in other cases. In
addition, 2005.09 DC seems to be a very stable release so far which is
in stark contrast to releases in the 2002-2003 range. The default in
DC is now the XG mode and this does save memory but still lags behind
Get2chip memory utilization by about 40-50%. Going forward it looks
like (keeping our fingers crossed as this release is still new) we will
be back to a mix of DC and Get2chip rather than just Get2chip as had been
the case over the past 1 yr or so. Don't you just love competition?
- [ An Anon Engineer ]
Tried Ambit a few years back. It was OK but clearly not priortized
by Cadence. See no real need to switch at the moment so no experience
with the others.
- [ An Anon Engineer ]
About the same as Get2chip but better than Ambit. Using Get2chip.
- [ An Anon Engineer ]
DC is ok. I am using Ambit now.
- [ An Anon Engineer ]
Using Synopsys now. Quite happy with it. Tried Ambit a long time ago.
It was crap.
- [ An Anon Engineer ]
Using dc_shell. Unstability aside (it's totally and absolutely imposible
for Synopsys to release a dc_shell version that doesn't have severe new
bugs....sigh), dc_shell gives you the flexibility to address any type of
design. Tried Get2chip, Ambit and Synplicity years ago. Other tools
perform "well" on specific design with particular flows, dc_shell performs
"average" everywhere, but it's reliable enough that you don't waste too
much time getting close enough to what you want.
- [ An Anon Engineer ]
DC 30% better results than BuildGates (Ambit). Using DC and Get2chip.
- [ An Anon Engineer ]
For us Ambit always generated better results than DC.
- [ An Anon Engineer ]
We are currently using Synopsys DC. Our group has tried Magma Blast
Create and don't think it is anywhere close to Synopsys DC. Personally,
I have invested a lot of time in Synopsys DC and think I know a lot of
the issues and their workarounds. I would rank it higher than most of
the other tools. I believe that at one time Ambit was better but
Synopsys caught up and overtook them a long time back. Cadence just
made too many mistakes on that.
- [ An Anon Engineer ]
So far DC is still superior but others are catching up quickly.
Use DC and PhysOpt.
- [ An Anon Engineer ]
They all synthesize. It is much more important to consider physical
aspects early in an integrated fashion. Therefore we rate Magma
Blast Create equal with they key advantage of being part of a fully
integrated flow. Parts of our users use
DC -> PhysOpt -> Blast Fusion
PhysOpt considers the physical aspects early, Blast Fusion discards
all those placements and starts again. Convergence/design closure is
however still good which shows that it is important to consider physical
information early. It is not so important which tool is used.
- [ An Anon Engineer ]
We're currently using Magma Blast Create.
- [ An Anon Engineer ]
We use both DC and Blast Create for cell-based designs, Synplicity for
Structured ASICs. My impression is that DC still gets as good (or better)
results than Blast Create.
- [ An Anon Engineer ]
In order of quality of results (includes gate count, performance,
power optimization, integration with backend):
1- Magma Blast Create
2- SNPS DC
3- Ambit
4- Cadence Get2chip
5- Synplicity ASIC
6- Incentia
We use 1 and 2
- [ An Anon Engineer ]
We switched a year ago to Magma Blast Create.
- Dinesh Venkatachalam of Legend Silicon
Using DC. Compared DC to Blast Create. DC seemed like the clear
winner. No desire to try others.
- [ An Anon Engineer ]
I have recently switched from dc_shell in favor of Magma Blast RTL.
Synopsys support is not worth risking your career on. Magma support
has been very effective at keeping productivity moving forward. Issues
are addressed quickly and accurately.
- John Schritz of Tektronix
DC is still the workhorse; Magma has had gobs of issues with logic
equivalency (i.e. synthesis bugs). If you're betting a career on
synthesis, stick with DC!
- Neel Das of Tallika Corp.
Going forward for smaller geometries tool having intergated flow with
synthesis and floorplanning would be more effetive. I am using Magma
Blast Create.
- [ An Anon Engineer ]
DC is near the top if not the top synthesis tool. There are classes of
designs that Blast Create might be better.
- [ An Anon Engineer ]
Design Compiler has improved significantly over the last two years;
mostly in part to the Magma competition. DC runtime, memory, area,
and QOR have dramatically improved.
- Lauren Carlson of StarGen Inc.
DC was first but now it is in middle of the pack. We are switching
to Magma.
- [ An Anon Engineer ]
Blast Create and DC are virtually tied depending on the test case.
Cadence RTL Compiler is third.
- [ An Anon Engineer ]
DC is the best out there. We use DC and Blast Create.
- [ An Anon Engineer ]
We have discontinued use of Design Compiler and have switched to Magma
and Synplicity. Synopsys is too expensive, provides poor support, and
does not service their customers well.
- [ An Anon Engineer ]
We are a DC-only house. Magma requires investing in the whole Magma
flow, and that's not an option for us. I would never consider
Synplicity ASIC -- I use it for prototyping our chip in FPGAs and see
the problems with it. I don't know Incentia. Haven't really given
Cadence a chance.
- [ An Anon Engineer ]
I mostly use Design Compiler. A little more than a year ago I tried
Synplify ASIC on my design, though not a rigorous apples to apples
benchmark. I tried synthesis with tight and with loose timing
constraints. In both cases, QoR was approximately equal to DC.
- [ An Anon Engineer ]
We use Design Compiler exclusively for ASIC synthesis and Synplicity
for FPGA synthesis.
- Nandakumar Natarajan of Agilent
Only ever used DC. Have heard that Synplicity ASIC is faster runtime
and sometimes better design.
- [ An Anon Engineer ]
We've tried Synplicity ASIC, but had some design issues, and no time
to resolve them. Our Synopsys scripts worked. We have maintained our
Synopsys licenses.
- Richard of Reindl of L-3 Communications
DC is still a robust logical synthesis tool, but the need is for physical
synthesis. Hence, for Structured ASICs we are doing timing closure (with
ideal clocks) using Synplicity's Amplify ASIC.
- [ An Anon Engineer ]
Synplicity
- [ An Anon Engineer ]
We use DC. I had benchmarked Synplicity ASIC, it seemed easier to set
up, but unfortunately didn't take .sdc's directly. As far as speed,
capability, area, timing, etc, they were very close, and with each
version I received, they leapfrogged (slightly) each other.
- [ An Anon Engineer ]
I only use Xilinx XST/ISE or Synplify. ISE is pretty slick, but
Synplify is easier to learn. For both, the help documentation could
use a little work with regard to directives.
- John Gedde of Aeroflex Laboratories
We're using Synopsys DC. In my last job, I did a 4 month long evaluation
of DC and Synplicity ASIC. AE's from both companies were helpful, Robert
from Synplicity was outstanding. He'd drop by to check on the runs, ask
about comparative data, and in general was technical, and helpful, and not
pushy with regards to the sale. The evaluation ended in a tie, both did
a good job of synthesizing a 2M gate 4M bit memory design, after both
companies did software updates. Synplicity was a lot easier to drive,
but didn't take the Synopsys constraints as is.
- [ An Anon Engineer ]
We will be using Cadence Get2chip.
- Mike Olson of Insyte Corp
We are just now deciding to replace most of our DC licenses with Cadence
Get2chip. We still feel the need to keep a DC license as a safety net
in case we see a performance swing on a crucial block nearer to tapeout.
- [ An Anon Engineer ]
We evaluated Get2chip and DC over several (6+) designs in our company and
saw comparable results between each tool. Some better with DC and others
better w/ Get2chip. Get2chip distributed computing capabilities is a nice
feature though. For some designs, Get2chip showed to be much better, that
is until you moved into PhysOpt. Results w/ Get2chip and DC as 'seeds'
seemed to even out the overall result.
Out of the box Get2chip is easier to use than DC, but seasoned users of DC
seem to be able to get better results.
We don't have much experience w/ Blast Create, but the TCL interface
and scripting looked appealing.
- [ An Anon Engineer ]
DC vs. Cadence Get2chip
DC Get2chip delta
Cell#...........94579.........88574..... 6.3%
Net#...........105663........101388..... 4.4%
Area: ..........1.45.........1.32...... 8.9%
Tcl Scripting and RTL Compiler constraining was straightforward and
intuitive. Runtime was shorter (not used DC XG mode). Get2chip
would be my preferred synthesis tool in the future.
- [ An Anon Engineer ]
We're currently using DC, because we have a significant amount of
scripting environment built around DC, and therefore is a lot of
inertia involved in changing to another tool. We have, however,
noticed that Cadence RTL Compiler is significantly faster than DC
and produces better results. Synopsys does, however, appear to have
got the message that they are in danger of losing customers to a
better product, and I think they're starting to catch up.
- [ An Anon Engineer ]
DC is dominant. Solid tool. Aging a bit, but that's not a bad thing.
- David Black, consultant
Using only Design Compiler, have not used anything else in 10 years.
I believe the quality of results with many of these tools is such that
any would be acceptable. The biggest issue is the availability and
accuracy of libraries. If using Primetime for signoff, then using the
same libraries for synthesis takes out one variable when trying to sort
things out.
That said, I think that Design Compiler (as well as most Synopsys tools)
has the look and feel of something klugded togeather. There is 0 thought
put into making this easy to use. The GUI is useful for selling the tools
to management in a demo, but are useless for getting the actual job done.
Clearly Synopsys feels they have enough of a monopoly that users have to
take whatever they dish out.
- [ An Anon Engineer ]
Design Compiler rank 1. We use Design Compiler.
- Chih-Hao Chung of Ali Corp.
We tried Get2chip, top-down flow, faster, less memory usage. But we
still use DC.
- [ An Anon Engineer ]
We use DC and Get2chip. Although we don't understand Get2chip as well
as DC we get very similar results to DC in a lot less time.
- [ An Anon Engineer ]
Get2Chip might be OK, but I don't trust Cadence acquired tools until
they have had them for a number of years and can prove they support them
properly. Ambit was OK a few years ago when I evaluated it, but it was
then apparent that they weren't supporting it properly and it has
subsequently fallen behind.
- [ An Anon Engineer ]
Compared recently Get2chip vs. DC, and found Get2chip not ready for use.
Still use DC Ultra.
- [ An Anon Engineer ]
We are using Synopsys DC, however the Cadence Get2chip is also picking up
momentum. Main reason I think is due to the fact that most customers are
really fed up with the degrading quality of DC. Every new version
introduces so many bugs that we are really questioning the QA department
of Synopsys.
- [ An Anon Engineer ]
Haven't compared, we use RTL Compiler
- [ An Anon Engineer ]
Reality for us is PhysOpt; DC/Get2chip are only quick estimates for
Verilog coders.
- [ An Anon Engineer ]
We are synthesizing with both DC and Cadence Get2chip RTL Compiler.
RTL Compiler saves area a lot more that DC. Most of our designs are
moving to Get2chip unless there's codes written in Module Compiler
which can not be transferred directly.
- [ An Anon Engineer ]
From 1 to 10 scale, DC is a 8.
- [ An Anon Engineer ]
We are using Design Compiler now. We are satisfied with it enough, so we
are not spending lots of time evaluating other choices.
- [ An Anon Engineer ]
We use Design Compiler. I have not run a comparison recently but I
believe that Cadence Get2chip may have an advantage. We would have
switched to this but the cost was way higher than we currently pay.
- [ An Anon Engineer ]
Cadence's Get2Chip is better. Fewer bugs, better results, better
support. That said we continue to mostly use DC due to being locked
in to the licenses.
- [ An Anon Engineer ]
use Cadence Get2chip and Synopsys Design Compiler
- [ An Anon Engineer ]
Using Cadence RTL Compiler. Get2chip has slightly better QoR on medium
to big designs.
- [ An Anon Engineer ]
Using Design Compiler. I think Get2chip is a tiny bit better on QOR.
- [ An Anon Engineer ]
We use DC, and haven't really used anything else.
- Tom Mannos of Sandia National Laboratories
We exclusively use DC - as it is well understood by all our designers,
has good run times, and can handle our design size.
- [ An Anon Engineer ]
We are using BuildGates for legacy modules and RTL Compiler for everything
else. We are happy with its performance and the benchmarks showed it is
better than DC.
- [ An Anon Engineer ]
DC is still the standard tool for synthesis. I have tried Cadence
Get2chip but not others. Use DC and PhysOpt for synthesis.
- [ An Anon Engineer ]
DC and PhysOpt are way better than Cadence PKS
- [ An Anon Engineer ]
I think Design Compiler is good despite there are bugs sometimes.
- Larry Ping of BroadLogic Network Technologies
Some people have done some eval on Cadence RTL Compiler. The result is
very impressive on runtime and simplicity, area reduction also show some
good result. Although we still use DC, but would keep very close eye
on RTL Compiler.
- [ An Anon Engineer ]
We have DC and Get2chip. It's a horse race. Get2chip may tend to give
less area, but DC has better and more mature "advanced optimization"
features.
- [ An Anon Engineer ]
We used Synopsys solely for synthesis until recently. We examined several
of the competitors: Blast Create, PKS, and RTL Compiler. We found RTL
Compiler (the old Get2chip solution) superior. It is far easier to use.
It does not fatal like dc_shell. It has a smaller memory footprint.
We are constrained by contract to continue buying dc_shell. This is
causing management heartburn. I guess time will heal this problem one
way or another.
- [ An Anon Engineer ]
Design Compiler rank against its rival Cadence Get2chip: slower, worst
QoR in general. Using both DC and Get2chip, will phase out DC next year.
- [ An Anon Engineer ]
DC has good user interface and good docs. Get2chip is better performance
and working time and design capacitance. Now we are using Get2chip.
- [ An Anon Engineer ]
We use Design Compiler - it works fine for us; we see no reason to change
to other tools.
- Sunil Malkani of Broadcom
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