( SNUG 05 Item 8 ) ----------------------------------------------- [12/20/05]
Subject: VCS, Vera, System Verilog, Formality, Magellan, DesignWare
SYNOPSYS STEPS UP -- Don't need to redo recent survey work on Synopsys
frontend tools when it's already in the DVcon'05 Verification Census.
The data from that report showed that Synopsys really stepped up against the
normally dominant Cadence in the verification space.
For Verilog/VHDL simulation use
Cadence 2004 total : ############################## 51%
Cadence 2005 total : ############################## 51%
Synopsys 2004 total : #################### 34%
Synopsys 2005 total : ############################ 47%
- from http://www.deepchip.com/items/dvcon05-02.html
For Vera vs. Verisity Specman 'e' use
2005 Cadence Verisity "e" : ################# 29%
Synopsys Vera : ################ 27%
- from http://www.deepchip.com/items/dvcon05-05.html
For IBM PSL & 0-in CheckerWare vs. Synopsys SVA & Vera OVA
2004 IBM Sugar/PSL : #################### 34%
0-In CheckerWare : ########## 18%
System Verilog SVA : #### 7%
Synopsys Vera OVA : #### 7%
2005 IBM Sugar/PSL : ############ 21%
0-In CheckerWare : ##### 8%
System Verilog SVA : ########### 18%
Synopsys Vera OVA : ####### 12%
- from http://www.deepchip.com/items/dvcon05-07.html
For Cadence Verplex vs. Synopsys Formality
2004 Cadence Verplex : ###################### 38%
Synopsys Formality : ################## 31%
2005 Cadence Verplex : ###################### 38%
Synopsys Formality : ########################## 40%
- from http://www.deepchip.com/items/dvcon05-12.html
For Synopsys Magellan vs. Mentor 0-in & Jasper
2004 0-In : ############################ 47%
Synopsys Magellan : ######### 16%
Jasper : ######### 16%
2005 0-In : ############### 26%
Synopsys Magellan : ################## 30%
Jasper : ###### 10%
- from http://www.deepchip.com/items/dvcon05-13.html
For Synopsys DesignWare vs. Cadence Veristy & Denali & Mentor
Synopsys : ################## 30%
Cadence Verisity : ############# 22%
Denali : ############ 21%
Mentor : # 2%
- from http://www.deepchip.com/items/dvcon05-17.html
For System Verilog
2005 "Do you see your project using System Verilog in the next 6 months?"
not in the
next 6 months : ######################S-S######## 81%
yes we will : ########### 19%
- from http://www.deepchip.com/items/dvcon05-04.html
But the recent Boston SNUG 2005 attendees reported
use Verilog : ######################S-S################ 94%
use VHDL : ############ 20%
use System Verilog : ######### 15%
use SystemC : ## 4%
And in 1 year they expect to
use Verilog : ######################S-S######## 80%
use VHDL : ########## 17%
use System Verilog : ########################## 44%
use SystemC : ##### 8%
Overall (looking at VCS, Vera, Formality, Magellan, DesignWare, and their
favored set of assertions) Synopsys verification use went up significantly
this year. In both surveys System Verilog gets 15% to 20% use currently,
with one projecting 44% use in 1 year. Not bad.
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