( SNUG 04 Item 7 ) ----------------------------------------------- [08/11/04]
Subject: LogicVision, Mentor TestKompress, Synopsys SocBIST
WERE'S WALDO? If you look at the user comments below, you'd be hard pressed
to explain these Dataquest BIST marketshare numbers:
Dataquest FY 2002 BIST Market (in $ Millions)
LogicVision ########## $10.4 (69%)
Mentor BIST ## $2.0 (13%)
Fluence BIST # $1.2 (8%)
Synopsys SocBIST # $1.0 (7%)
other $0.3 (3%)
Why? Because I got lots of Mentor and Synopsys BIST user chat here, but
hardly any LogicVision user talk! That doesn't make sense for a tool that
supposedly has 70% marketshare. I went to the web to see how LogicVision
was doing. The Yahoo stock page says they've been losing money for the
past 3 years! Whoa! "LogicVision, even though they have 70% marketshare,
has had a very low profile for the past 2 years," Gary Smith of Dataquest
told me. "They need something to get their company back off the ground,
especially with the importance of BIST in the DFM arena."
Other than MBIST Architect, we are very happy with the Mentor DFT
suite and would definitely recommend it to other engineers. We have
noticed that the Mentor tools seem to have the lowest learning curve
of any DFT tools in the market.
TestKompress: version 2004.3
FastScan users take no more than 2 days to come up to speed with
TestKompress. We have seen very good results with TestKompress in the
area of gate count, usability, flow and the data and test time
compression provided. One of our designs was 3 weeks from tape-out
when we interrupted it to add TestKompress. Despite being timing
closed and having to open up the database to break up the scan chains
into shorter chains, we delayed the tape-out by only 2 weeks. Silicon
passed all the test vectors on the tester within a week of getting on
the test floor.
TestKompress' biggest strength - ease of use and very good flow. On
one of our cores, we have seen stuck-at coverage of 99.4% with a very
low pattern count and run time of a couple of hours. For at-speed test
on the same core, we have seen 89% coverage with a moderately low
pattern count, compared to other tools in the market with a run time
of ~12 hours, which again compares very favorably with other tools
in the market.
MBIST Architect: version 2004.3
MBIST Architect seems to have about 1 weeks worth of learning curve.
It is possibly the only Mentor DFT product that still needs to be
improved. The gate counts are still pretty high and we still have a
very high bug detection rate in it. The QC process for this tool
needs to be improved because a bug in the MBIST structure means a
hardware change and is not as easy to fix as a software bug.
- Denzil Fernandes of Texas Instruments
I have not tried any of the BIST tools except for a brief try at
TestKompress. TestKompress requires design and layout effort that will
impact the design schedule and we didn't have the people or the time to
pursue TestKompress on the current design I am working on.
- [ An Anon Engineer ]
I noticed you didn't include Mentor's LBIST Architect tool in your list
of BIST tools, and I thought it should be mentioned. We've successfully
taped-out a half-dozen ASICs with logic BIST implemented with this tool
over the last couple years. Design sizes were as large as 4M gates
(not counting memories), with in-system test coverage typically
exceeding 98% from BIST alone, higher when augmented with FastScan.
A couple of the larger chips were bisted at the block level so that
multiple instances of the same block could be reused in layout. So we
actually have silicon for over a dozen unique bisted entities and we've
never had a problem with the actual signatures not matching those
predicted by LBIST Architect. There was a bit of a learning curve at
first, and we typically modify the RTL produced by the tool somewhat to
meet our particular requirements, but in general we're pretty happy
with it. When run at-speed, we also get better transition fault
coverage with LBIST Architect in far fewer cycles compared to the
transition coverage results using ATPG only.
TestKompress and Synopsys SocBIST don't fit our definition for BIST
since they both require extensive stored patterns to be applied to the
chip by external means. Our main driver for the use of BIST is
in-system coverage, both for safety and ease of diagnosis. In our
applications BIST needs to run off a system clock with no other
external stimulus while running and can be invoked either from boundary
scan or from a CPU interface.
- Jeff Geneser of Rockwell Collins
Our flow uses the Synopsys SocBIST XDBIST by default now. Deterministic
BIST is essential to keep high the coverage. Anyway the licence for
DBIST is very expensive.
- Massimo Scipioni of STmicroelectronics
TestKompress: a great tool. But not right price. Performance is also a
question. Can not support large design styles and flows. For example,
how to efficiently take the advantages of many identical cores/blocks.
MemBIST Architect: does not support RTL insertion correctly. It needs
to have more knowledge on ASIC design flows and styles to handle this
correctly. This is always a problem. The gap between EDA and ASIC
design community becomes larger and larger.
LBIST: only works as an academic toy. Cannot accept industrial design
assumptions.
BSDArchitect and FlexTest: don't use them very often.
- Xinli Gu of Cisco
We have never used commercial BIST tools except in ASICs and people
that used LogicVision were quite comfortable. No idea as to how
Synopsys or Mentor or Syntest stacked up against LogicVision. BIST is
so straight forward to code and implement as part of the design, I am
not really excited about EDA vendors providing BIST support unless
they can give guranteed coverage results, and repeatability (with
logic BIST).
- Vasu Ganti of Sun Microsystems
On my last chip I used the DesignWare memory BIST controller with my
memory collar. Before that chip I used my own mem BIST controller as
well. I have traditionally used my logic BIST controller in conjunction
with the DC inserted scan chains and JTAG. We evaluated the Mentor and
LogicVision tools last year. We tried to understand where Synopsys was
going in the DFT world. LogicVision won.
- Ron Range of Raytheon
BIST is intrusive, while the TestKompress not so much. We don't have a
tester memory limit, yet, so neither is required at this time.
- Larry Tesdall of QLogic Corp.
Our comparison of Mentor TestKompress and Synopsys SocBIST found them
to be equivalent.
- [ An Anon Engineer ]
For BIST, Mentor TestKompress is the more elegant of the solutions in
my opinion and would be my preference, all business reasons aside.
Synopsys SocBIST does have more capabilities in terms of full logic
BIST versus just compression, but since we don't care about the full
logic BIST it's a non-point. Synopsys currently creates timing loops
(they are in the process of fixing this) in SocBIST which I feel is a
bad joke. Further, TestKompress has a better history than SocBIST as
its been around much longer.
- [ An Anon Engineer ]
We've used LogicVision, and Synopsys SocBIST. They compliment each
other. We've yet to see if the SocBIST works out all right on silicon.
- Haiming Jin of Intel
LogicVision is a pain-in-the-ass to deal with, though a few of our
designs use it. We use a custom TAP block for all other designs to
address Serdes test, internal RAMs with built-in-BIST, etc. Moving to
external RAMs, still have Serdes test issues, will keep internal TAP.
Synopsys SocBIST is a poor solution crafted to fit between everybody
else's patents. Mentor TestKompress looks nice, but $$$.
- [ An Anon Engineer ]
We use LogicVision, Synopsys DFT Compiler and TetraMAX.
- David Fong of S3 Graphics
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