( SNUG 04 Item 6 ) ----------------------------------------------- [08/11/04]
Subject: Synopsys DFT Compiler/TetraMAX vs. Mentor DFT Advisor/FastScan
IT HELPS TO HAVE RICH RELATIVES: In any design, there are two major parts
to testing. Inserting a scan chain into your chip and then creating test
patterns to feed into those scan chains you just inserted.
Dataquest FY 2002 Scan Insertion Market (in $ Millions)
Synopsys DFT Compiler ################################# $26.6 (96%)
Mentor DFT Advisor # $0.8 (3%)
other $0.3 (1%)
Even though Mentor trys to play here, Synopsys rules the scan insertion
market. Why? Because scan chain insertion is so very close to synthesis
and Synopsys owns 90% of the synthesis market. It's easy to find money if
your daddy's Bill Gates!
Now on the ATPG side there's no technology monopoly influencing the battle:
Dataquest FY 2002 ATPG Market (in $ Millions)
Synopsys TetraMAX ############# $10.6 (45%)
Mentor FastScan ############## $11.3 (48%)
other ## $1.7 (7%)
So in a fair fight, Mentor FastScan and Synopsys TetraMAX are each doing
roughly half and half each in the ATPG market.
2.) What dou you think about the Synopsys DFT Compiler/TetraMAX vs.
Mentor DFT Advisor/FastScan battle? Which one(s) do you specifically
use on your project? Who's winning? Who's losing? How about BIST
like LogicVision, Mentor TestKompress, Synopsys SocBIST, SynTest?
Who's ahead and who's behind? Which do you use?
We use DFT Compiler/TetraMAX. We've also used FastScan. FastScan is
good. However, it is convenient to have TetraMAX pick up STIL files
from DFT Compiler. TetraMAX doesn't seem to support Verilog-XL well,
which is kind of awkward and surprising.
- Haiming Jin of Intel
I think DFT Compiler is better tool to use, especially if combining with
PhysOpt. Placement-based scan stiching/re-ordering can be done under
the same hood.
- [ An Anon Engineer ]
FastScan: version 2004.3
Our FastScan users have come up to speed in as little as a month. We
have seen very good results with fault coverage and runtime and the PLL
support features are excellent. The pattern count is something that
possibly can be worked on. FastScan's biggest strength is its high
coverage and good run time.
For TestKompress/FastScan, the pattern count for at-speed testing can
still be improved. Other tools in the market have a slightly steeper
curve with respect to number of faults detected and pattern count
DFT Advisor: version 2004.3
DFT Advisor seems to have about 1 weeks worth of learning curve. It's
biggest strength is very good error messages, making it very easy to
debug scan related failures.
Flextest - version 2002.3
Flextest possibly has the longest learning curve but it is also a more
complex tool than any of the others in terms of what it does. Given
that we all are full scan these days, we only seem to use Flextest to
fault grade our functional patterns -- which is why we have not used it
much in the last 2 years. Flextest biggest strength is very good
support for fault grading.
- Denzil Fernandes of Texas Instruments
We used in the past DFT Advisor/FastScan flow. Now we integrated
DFT Compiler into our flow. It makes much more sense because we use
DC, so DFT Compiler is seamlessly integrated, but we still use
FastScan. We are going to evaluate TetraMAX in a short while. (We
are still happy with FastScan, though.)
- Juan Carlos Diaz of Agere
I don't have enough time to write all I would like to say about DFT
Compiler. If PhysOpt gets a 1 (out of 5) on my scale of "EDA tool
goodness" then DFT Compiler gets about a -3. Horrible! And we're only
trying to get it to *insert* scan, not even do ATPG or anything
remotely complex!
- [ An Anon Engineer ]
We use Mentor test tools for the most part. We are pushed into using
Synopsys DFT Compiler when a design is using PhysOpt because of the
integration and, therefore, QoR benefits.
- Andrew Bell of PMC-Sierra, Inc.
We use Synopsys DFT Compiler and TetraMAX, which are better integrated
in our Synopsys based design implementation flow.
- Marcello Vena of Xignal Technologies AG
DFT Advisor: was a great tool to be used for scan insertion before. But
with design technologies and flows being changed, it cannot follow the
same pace. Major issues: it needs a true one-pass scan insertion flow
combining with synthesis and physical design together. Secondly, truely
support hierarchical design flow. Thirdly, we cannot wait for a few
weeks with more than 10 Gb CPU memory usage for scan insertion.
FastScan: Still pretty competitive in terms of coverage, # vectors and
CPU time usage. Has some problems in supporting multiple-detection
flow. Many useless commands and illegal commands are still accepted by
the tool causing a lot of confusion
- Xinli Gu of Cisco
I have used both Synopsys DFT Compiler and Mentor DFT Advisor to insert
scan. I had been using DFT Advisor for scan insertion because it has
slightly better control when inserting scan, but I had to use DFT
Compiler because DFT Advisor crashed (segmentation fault) repeatedly
and was unusable for scan insertion on portions of my design. Mentor
has been slow in providing a fix for this segmentation fault (it has
been months with still no fix). A major problem with DFT Compiler is
the extremely slow (hours to days depending on size) load times for
Verilog gate netlists. Supposedly Synopsys is fixing this, but I have
not seen the fix yet.
DFT Compiler can be easier to set up because it detects clocks
automatically in the netlist, however if you only want specific clock
domains to end up on the scan chain, then DFT Advisor works better
since you explicitly tell it what ports are clocks and only flops
attached to those ports are placed on the scan chain. Also DFT
Compiler is more strict (i.e. won't allow) on assigning the scan enable
attribute to signals that may have already been picked up by DFT
compiler as going to sequential logic.
I use FastScan for the scan vector generation and have not used
TetraMAX, but from talking with people who have tried both, FastScan
gives better results in a shorter amount of run time and most, if not
all the people in my group use FastScan.
- [ An Anon Engineer ]
When Synopsys pulled test from DC, I stopped using them. We now use
Mentor DFT products in our flows.
- Gord Allan of Carleton University (Canada)
We are using DFT Compiler and TetraMAX for last three years and happy
with it.
- Harish Dangat of Cypress Semiconductor
We just bought Mentor FastScan. The tool is flexiable and supports
different scan methodology. It also has very good debugging features.
- Joe Dao of Aeluros, Inc.
I evaluated TetraMAX, Mentor FastScan, SynTest last year. Performance
side, SynTest wins.
- Can Ma of Spreadtrum Communications (China)
We use Mentor FastScan.
- [ An Anon Engineer ]
We had invested a lot of resources on in-house test tools (scan
insertion, ATPG, fault location etc) for past few years because we
thought the off-the-shelf tools were not quite there. Our internal
tools could handle CTAG (the Philips version of JTAG), hierarchical
testing, fault location, etc. much better.
Based on our recent evals we have switched our test tool flow to
DFT Compiler because of its very tight coupling to PhysOpt at the
frontend and to TetraMAX ATPG at the backend. Using DFT Complier
along with PhysOpt has helped us avoid handoff problems between
logic synthesis, scan insertion, and P&R tools.
- Arvind Chopra of Philips Semiconductors
Synopsys is behind. I had been using DFT Compiler and BSD Compiler to
get scan chains and JTAG in the chip.
- Ron Range of Raytheon
We use DFT Compiler and for what we want it's fine.
- [ An Anon Engineer ]
Used TetraMAX on last project - actually DFT was done by the Toshiba
ASIC backend team.
- [ An Anon Engineer ]
I am using DFT Compiler and TetraMAX, AND will change to Mentor tools.
- [ An Anon Engineer ]
I am using DFT Compiler with TetraMAX.
- Massimo Scipioni of STmicroelectronics
Moved from FastScan to TetraMAX for most designs about 2 yrs ago.
TetraMAX has functionality needed for our scan compression that
FastScan does not. TetraMAX wins between this pair. Moving forward,
we're migrating our internal compression methods to Cadence's
(ex-IBM's) OPMISR and consequently will be using Test Encounter
(or whatever it's called) for vector generation. Synopsys
DFT Compiler does not handle hierarchical designs appropriately; all
of our designs are hierarchical and have been forever. We use a custom
solution for test insertion.
- [ An Anon Engineer ]
We have both licenses, FastScan, and TetraMAX. We used TestGen (pre-
TetraMAX) in the past and now use FastScan. I think they are all
pretty much similar if one were to look at a typical ASIC application.
All the vendors have tools that are easy to use. All the tools provide
decent coverage for vector ratio. Similar performnce (haven't really
done any comparisons in the last 4 years). And the support structure
is similar, too.
That said, I was looking to see if there were any inroads being made
into increasing test coverage without increasing test vectors, and
Synopsys has definitely done stuff in this regard. I was also
interested in tools that could easily understand the internal clock
generation schemes to be able to apply AC tests (delay path or
transition) and once again, Synopsys seems to have stuff in this area.
- Vasu Ganti of Sun Microsystems
DFT Complier vs DFT Advisor:
DFT Compler is prefered for designs being synthesized with DC. RTL
rule checks catch problems early. Scan insertion as part of synthesis
reduces complexity of overall flow. Gate level rule checks augment
the ATPG tool rule checkers.
TetraMAX vs FastScan/Flextest:
For full (combinatorial) scan TetraMAX and FastScan are both quite
capable. Improvements in compression and runtime differentiate releases
of each tool. FastScan/Flextest has some advantages with respect to
sequential pattern generation through non-scan state elements, although
TetraMAX is improving. Strict enforcement of "full-scan" design rules
reduces the need to use partial scan algorithms. As device sizes
increase it is becomming easier to enforce full scan design rules.
- [ An Anon Engineer ]
We are currently using FastScan, but evaluating Cadence Encounter.
Encounter looks very favorably against FastScan. FastScan has some
features such as name capture procedure for AC testing, but Encounter
still does better in path delay testing.
- Jing Zeng of Motorola
We're using Synopsys DFT Compiler for scan insertion and TetraMAX for
ATPG. On our current project we have eventually succeeding in running
hierarchical scan insertion. It took us a while and there are still a
few snags (for instance one cannot guarantee the scan segments order
from one run to the next). We're looking at logic BIST (we're already
using memory BIST) for the next project.
- [ An Anon Engineer ]
TetraMAX is doing well. They have better understanding of timing issues
that involve transition delays. This is a key differentiator. Don't
know who's winning, but we would use TetraMAX again over FastScan. High
fault coverage, at-speed testing will become more and more important.
- Larry Tesdall of QLogic Corp.
DFT Compiler is junk when it comes to latch based design. FastScan can
do latch based design with ease.
- Abraham Si of Maxim Integrated Products
We use Synopsys DFT and TetraMAX. Haven't compared them vs. Mentor
DFT Advisor/FastScan.
- [ An Anon Engineer ]
We at Intel use our own technqiue called X-Compact & XPAND. X-Compact
is an X-tolerant test response compaction technique that is used for
compacting outputs from scan chains. XPAND is a test stimulus
compression technique that is used to compress test patterns. X-Compact
is being used by roughly around 30 products now and XPAND by roughly
around 15. These schemes had been essential in reducing test data
volume/test time. The advantages of these techniques are clear, and
these techniques have been presented at several conferences (ITC 2002,
ICCD 2003, VTS 2004)...
Here are a few references for the interested readers:
Mitra, S., and K.S. Kim, "X-Compact: An Efficient Response Compaction
Technique for Test Cost Reduction," Proc. Intl. Test Conf.,
pp. 311-320, 2002.
Mitra, S., and K.S. Kim, "X-Compact: An Efficient Response Compaction
Technique," IEEE Trans. CAD, Vol. 23, Issue 3, pp. 421-432, March 2004.
Mitra, S., and K.S. Kim, "XMAX: X-Tolerant Architecture for Maximal
Test Compression," Proc. IEEE Intl. Conf. Computer Design, 2003
- Subhasish Mitra of Intel
I think for the FastScan/TetraMAX tools, they are close to equivalent.
Either works well and Synopsys has a pretty good history with TetraMAX.
- [ An Anon Engineer ]
We use DFT Compiler since it is tied to DC
- Sunil Malkani of Broadcom
We use DFT Compiler, largely for integration (easier scan chain re-
ordering). Used to use DFT Advisor, but it seemed Mentor had put
that on life-support.
- [ An Anon Engineer ]
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