( SNUG 04 Item 5 ) ----------------------------------------------- [08/11/04]
Subject: Design Compiler vs. Cadence Ambit/Get2chips, Synplicity ASIC, Magma
THE NEVERENDING STORY: If you look at the last available Dataquest numbers
for RTL synthesis market share (2002), you'll find:
Dataquest FY 2002 RTL Synthesis Market (in $ Millions)
Synopsys DC ######################################### $132.7 (90%)
Cadence Ambit ### $8.8 (6%)
Synplicity ASIC # $2.9 (2%)
Get2chips # $2.9 (2%)
In the 10 years that I've been writing SNUG Trip Reports, that Synopsys
market share has only fluctuated from 87% to 91% -- with the 3 or 4 rivals
left fighting over the remaing 9% to 13% of the market. What's the Synopsys
secret? They're paranoid about keeping Design Compiler a Best-In-Class tool.
Whenever it loses a customer benchmark anywhere, Synopsys R&D jumps all over
it to figure how they lost and then fixes Design Compiler in next rev. So
in a weird way, Synopsys and DC users owe a big thank you to Cadence, Magma,
and Synplicity for helping to keep Design Compiler constantly improving. :)
1.) In his SNUG keynote address, Aart claimed Design Compiler 2003.12
runtime had sped up 50%, areas were 5% smaller, and DC gained 20% in
capacity. In your experience as a hands-on user, is Aart lying or
telling the truth here? How does Design Compiler stack up against
its rivals Cadence Get2chip, Ambit, Synplicity ASIC, Magma Blast
Create, Incentia in your eyes? Which synthesis are you using now?
We stick with Synopsys for synthesis. It is our "corporate standard".
Although I use the older 2003.06 version since that is what my ASIC
vender recommends.
- Ron Range of Raytheon
We use DC.
- David Fong of S3 Graphics
I am using DC 2003-12, but I think that the best innovative changes
will come from other companies. Probably Cadence Get2chips of Magma
Blast Create.
- Massimo Scipioni of STmicroelectronics
Regarding the competition, I have the impression that Cadence buying
Get2Chips has had a very positive influence on the performance of
Design Compiler. We use only Design Compiler.
- Pierre Ragon of Lucent
We are using Magma Blast Create in production. We taped out a chip and
had working silicon using Magma. No experience with latest DC.
- Joe Dao of Aeluros, Inc.
We are currently comparing DC against Blast RTL. Blast RTL achieves
similar to better results when taking it through the Magma flow.
- [ An Anon Engineer ]
For the last 9 months, we have started using Magma's RTL synthesis and
we just finishing our 1st and 2nd chips (2500/4000v K Gates, 166/200 MHz
respectively). Here is what we observed:
- Synthesize our entire chip in under 5 hours on a 32-bit Linux box
using one license. Switching to Blast Create was a no-brainer
because its two more steps beyond using Blast Fusion. For those
who understand the Magma flow, all we need are 'fix rtl' and
'fix netlist' in Blast Fusion script. One script makes the chip!
- We trust the ESP report to decide when we are ready for P&R. Our
internal guideline is for ESP value of 4% or less. Most important,
there are no SDF backannotation runs of synthesis, and no more long
debug sessions of tracing timing paths in layout.
- We are a small and efficiency-conscious company. 3 design engineers
turn out the full RTL to GDS in 12-15 weeks. We migrated all of
our cumulative knowledge of using DC in just under a month.
- We still ran into problems. One formal error showed up and two
crashes. All were resolved within a week. But no show stoppers.
How about improving its error messages? Give me more PT-like constraint
writing capabilities. Generate information such as constant-setting for
formal verification. I have my list and I use that every time Magma AE
needs a little reality dose.
- Phil Brennan of WIS Technologies, Inc.
DC does seem to keep up with other products in QoR, but there are some
versions that are buggy. I would not expect this from a product that
has been in the running for nearly 10 years.
- Sunil Malkani of Broadcom
We use Synopsys DC. Never took seriously these marketing claims.
Never had time to compare against others, though.
- [ An Anon Engineer ]
We use Design Compiler exclusively. We tested Ambit a while back but
didn't find that it had enough advantadge over DC to justify the switch.
- [ An Anon Engineer ]
We use DC. We don't see that kind of improvements here. I don't have
an opinion on the capacity issue though. We don't stress that end.
I have no opinion on other tools except Ambit. Ambit seems less mature
in many areas, though it is fast and delivers comparable results in
straightforward designs.
- [ An Anon Engineer ]
Comparing DC pre-2003.12 to DC 2003.12 -- Yes, 2003.12 is a significant
improvement. We've been able to move from ACS to a top-down compile on
a major design partition, which is quite a gain.
DC vs. Ambit:
Ambit's timing engine (CTE) is an awful lot faster than DesignTime,
giving much better timing report run times.
For Design 1, area was 31% better for Ambit. WNS (as measured by
reading both the DC netlist and Ambit netlist in to DC) was 15%
better, TNS was 16% better. DRC was slightly better for Ambit. Run
time was about the same, with memory use 44% better in Ambit.
Design 2 had problems. The distributed compile mode of Ambit (the
equivalent of ACS) failed to work properly on site. Ambit also had a
bug which prevented scan insertion working correctly in distributed
compile. Thus we had to run the compile top down, which gave a
runtime of over 80 hours! I didn't try to do the same thing with DC
as it simply wasn't practical and so isn't a meaningful comparison.
Formal verification (using Formality) of the Ambit generated netlist
failed on Design 2, due to what we later discovered was a bug in the
Ambit Verilog front-end. There were some other differences between DC
and Ambit interpretation of Verilog that caused some fun in equivalence
checking -- e.g. watch out for the way Ambit deals with bit selects
out of range.
Some Ambit usability comments:
- Ambit contains what Cadence say is a sign-off quality timing engine
(CTE), so you've no need to load the netlist in to PrimeTime if your
vendor supports CTE.
- Ambit's do_optimize automatically time-budgets when you're doing a
hierarchical compile, which obviates the need for an ACS style flow.
This is cool, but it does mean you have to flatten the design
hierarchy if you don't want this to happen.
- Ambit has a report_timing -false_paths command. Nice.
- Ambit uses a default "asynchronous" clock (called "@") if you don't
specify a clock in your constraints. DC searches for the most likely
clock. This means the constraints may be interpreted differently if
you don't specify clocks in all cases!
- check_timing can swamp you with false warnings if a signal is clocked
by both a virtual and real clock.
- there's no equivalent of the "link" command in Ambit! Optimize will
happily work for hours on a design, only for you to find big chunks
are missing.
- DC can choose a different DesignWare architecture at any time during
compilation. Ambit picks an architecture during initial mapping and
this remains unless manually changed.
Overall conclusion was Ambit looks promising, with better capacity and
QOR. However, too many problems for us to use at the moment.
- [ An Anon Engineer ]
We use Ambit. In a test of our 12k instance design it yielded a reduced
instance count. BuildGates Extreme did a better job at reducing the
power, although we didn't get a fair comparison there so I can't read
too much into this. We primarily chose Ambit because Cadence would rent
it to us for the 2 weeks, twice a year when we need it.
- Brett Warneke of Dust Networks
We don't use this version of DC yet; we are still at 2003.03. Ambit
appears to have similar performance, but fewer features and, of course,
people are used to Design Compiler. If your future messages confirm
the DC 2003.12 advantages, we may have a look at it.
- [ An Anon Engineer ]
I've used DC and Ambit/PKS interchangably for a few years now. I've
found Ambit tends, on average, to be slightly faster. Depending on the
circuit I've seen marked differences in area/timing performance. On a
combinational LUT (10x256) for a DDS, DC would churn for hours and often
spit out circuits which were signficantly less efficient than on
previous runs, with the exact same scripts. It became a black art to
try to reproduce the same design twice.
With regards to specific Ambit/DC comparison, on a 32-bit signed
multiplier benchmark, optimized for area with extremely lax timing
constraints, DC was twice as big as Ambit. Using the DesignWare
component, DC was 10% larger than Ambit. On different designs though,
I've seen Ambit choke where DC runs away with it. I haven't been able
to isolate what the key circuit differentiators are which cause one of
them to perform much better than the other.
- Gord Allan of Carleton University (Canada)
I have not bench marked DC 2003.12. We used 2003.06 for our last
design. I also extensively compared Get2chips against DC. Overall for
the same technology and RTL:
- Get2chips was 0% to 5% better in area.
- In terms of timing, both met goals.
- In terms of runtime, Get2chips was a solid winner.
- Tool output was much well organized from Get2chips.
- Biggest deal with Get2chips was not to be able to save a design
in binary (db) format. One had to write out Verilog and constraints
and rely upon read-in of Get2chips.
We ended up using Design Compiler, because by the time the Get2chips
eval came by, we had enough investmented in automating synthesis with
Design Compiler that we did not want to throw it away.
- Deepak Lala of Cisco Systems
We're currently using Synplicity ASIC. 3-5 years ago I ran a comparison
between Synplicity and Synopsys. Synplicity won easily for speed and
performance. Plus Synopsys support and local FAE were terrible as well
as arrogant. Even if Aart is telling the whole truth (I'd guess he's
cooking the numbers or using best case scenarios to make his numbers
look better), its still not good enough to go back to Synopsys.
- John Snick of Motorola
We used Synplify ASIC in three types of chips, small/medium versions
(400/900 K gates), and bigger version (1.5M gates). The tool could not
handle the bigger version due to capacity, so we stopped evaluation
until Synplicity can upgrade their tool to handle the big capcacity.
The smallest version was easy and we taped out the chip without
problems.
Regarding the medium testcase see following issues:
1. Fast engine, as it quickly finishes synthesis (within 2-3 hours)
2. Quality of netlist produced is not great, as it does not map well
when doing formal verification (in our case LEC). We had to do
enormous amount of mapping to improve the hierarchical LEC.
Synplicity has been able after a while to provide the mapping,
and solve the problems.
3. User-friendly GUI with easy methods to run several project options.
4. Hierarchy maintain was supported but had few bugs when we turned on
this option. We had to maintain it due to logic simulations and STA
constraints verification. Again, Synplicity has worked hard to fix
this problem.
Overall, the tool has a very powerful fast engine, and supports various
synthesis techniques especially for arithmetic functions. But, it's
still not mature enough to work well with other tools and standard
formats, and can not handle big capacity yet.
- Hatem Yazbek of Oplus Technologies (ESNUG 422 #5)
I was very impressed with Synplify ASIC's performance. It performs a
top-down synthesis of our design in one hour flat. DC 2003.03, on
the other hand, takes a little more than 6 hours to perform a top-down
synthesis. Iterating on synthesis is much less painful using Synplify
ASIC because of the greatly reduced runtime.
- Darren Lasko of Fujitsu (ESNUG 422 #5)
We use Synopsys Design Compiler for ASIC synthesis. While Synplicity
has done a great job of addressing the specific needs of the FPGA
community, we decided to stay with the tool with which we are most
familiar when designing ASICs.
- Mike D'Jamoos of White Rock Networks (ESNUG 393 #3)
DC runtimes are still horrific compared to Get2chips & Synplicity ASIC
and, of course, memory usage by DC can't even compare to its rivals.
DC is the biggest memory hog around (often 5x of what others take).
In terms of area results it seems like Synplicity ASIC _may_ be the
best, on average, based on only 2 good test cases I've run. (OK, with
2 test cases, it's hard to say yet). Get2chips seems to rule the roost
when it comes to timing critical designs. However we do see cases
where DC-Ultra still beats Get2chips. Synplicity ASIC so far did blow
up on the one timing critical design we threw at it, but that could be
a fluke. Don't know yet.
Basically, our recent experience has shown that synthesis has definitely
become a commodity and Synopsys has a lot of work to do if they want to
remain on top. They suppossedly have this new XG mode in DC which
improves things in 2004.06, but we have yet to test it.
- [ An Anon Engineer ]
I think Synopsys is better than Ambit or Get2chips.
- Abraham Si of Maxim Integrated Products
DC 2003.12 has a lot of false warning messages. I didn't see area
improvement. About speed-up may be a little. A whole day job didn't
reduce to half day job, though I wish it to. Synplicity ASIC is
getting be better and stronger.
- Can Ma of Spreadtrum Communications (China)
The DC syn_vV-2003.12-SP1 has a huge bug that we have to go back to
syn_U-2003.03. However, we did compare the DC syn_vV-2003.12-SP1 and
Cadence Get2chips. DC ran 8 times faster and had a slightly smaller
netlist. We evaluated Synplicity ASIC because we use Synplicity for
FPGA. The Synplicity ASIC is too primitive for ASIC design.
- Edmond Tam of Global Locate, Inc.
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