( SNUG 04 Item 3 ) ----------------------------------------------- [08/11/04]
Subject: VCS, SystemC, System Verilog, Synopsys Formality, Magellan, DW
BEEN THERE, DONE THAT: Don't need to redo recent survey work on Synopsys
frontend tools when it's already in the DVcon'04 Trip Report.
Item 1: the DVcon'04 Bigwig's Big Speech
Item 2: Modelsim, VCS, NC-SIM, Aldec, Icarus, SynaptiCAD, Wellspring
Item 3: SystemC
Item 4: System Verilog
Item 5: Verisity Specman "e", Synopsys Vera, SystemC SCV, JEDA
Item 6: IBM Sugar/PSL, 0-in Checkerware, Verplex OVL, System Verilog SVA
Item 7: TransEDA, Atrenta Spyglass, Novas Debussy, Verisity SureCov
Item 8: Summit Visual Elite, Mentor HDL Designer (Renoir)
Item 9: Cadence Verplex, Synopsys Formality, Mentor FormalPro, Prover eCheck
Item 10: 0-in, Jasper, Synopsys Magellan, RealIntent Verix, Averant, @HDL
Item 11: Cadence Palladium, Verisity Axis, Mentor IKOS & Celaro, EVE, Tharas
Item 12: Mentor Seamless, CoWare ConvergenSC, Annapolis CoreFire, Summit VCPU
Item 13: Synopsys DW AMBA, Denali PCI Express, Verisity USB
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