( SNUG 03 Item 13 ) ---------------------------------------------- [05/14/03]
Subject: LogicVision BIST, Mentor TestKompress, Synopsys SocBIST, DBIST
NEW KIDS ON THE BLOCK: One of the quiet pieces on Synopsys news this year
is their first serious jump into the BIST market. Deterministic Logic BIST
(called DBIST for short) and their SocBIST. At first blush, it appears that
X's are causing problems for the newbie Synopsys BIST tools; issues that
LogicVision and Mentor's TestKompress users don't complain about. There's
nothing like being new to a market. :)
Dataquest FY 2001 BIST Market (in $ Millions)
LogicVision ############ $12.0 (72%)
Mentor ### $2.8 (17%)
Fluence # $1.3 (8%)
others . $0.5 (3%)
"SocBIST Introduction
Synopsys SocBIST is of type deterministic logic BIST (DBIST). SocBIST
enables much smaller ATPG vector set to run at-speed tests at much
faster speed and reduced tester and testing costs.
DBIST (Deterministic BIST) is in contrast to other Logic BIST (LBIST)
such as the tool provided by SynTest. LBIST runs Pseudo Random Pattern
Generation (PRPG) from seeds for millions of cycles to complete tests.
However LBIST has problems of: hard to integrate into synthesis flow,
need BIST expertise, lack of predictability (hence no guarantee of test
coverage, problem for DFT closure, and often needs top-off ATPG
patterns), poor failure diagnostics, and inefficient use of testers.
DBIST is well integrated into DC (and PhysOpt) environment. Since it
understands the design, it can pre-determine the bits that can detect
some particular faults with one pattern only while this may be missed
by LBIST or it will take lots of cycles for LBIST to detect.
SocBIST consists of CUT (Circuit Under Test), a PRPG, an Output
Compaction and Comparator, Anti-Aliasing Logic (prevent two faults from
canceling each other) and a Controller. The CUT contains massive scan
chain parallelism (up to 512 parallel chains). The entire CODEC
structure can have 20k-50k registers. If total register counts go up,
it will require additional CODEC. Each CODEC adds additional 10 pins.
Only one controller is required. The sweet spot for SocBIST is 20k
registers. It is hard to justify BIST logic overhead for small designs
with less number of registers.
SocBIST is integrated into DFT Compiler & TetraMax ATPG 2003.03 rev.
The hard coded part of SocBIST should be improved."
- Bo Gao of Cypress Semiconductors
"As for BIST, forget LogicVision and Syntest, they have a ways to go.
DBIST has a good potential but would have to become X-tolerant and at
the same time provide very high pattern compression (almost as good
as DBIST) which Mentor's TestKompress does have. The other advantage
on Mentor's side is that the amount of logic used can be less."
- Amit Sanghani of Nvidia
"We used SocBIST tool from Synopsys. We didn't use the complete flow.
That means I didn't use DFT Compiler to generate the IP, nor do
insertion of scan chains, nor DBIST IP, etc. We did all that on our
own.
We got the IP from Synopsys and then we used TetraMAX in DBIST mode.
The main problem with DBIST was that we had to get rid of all sources
of dont-care's and unknowns. This turns out to be quite a bit of work
if there is some amount of logic which would need to be added to take
care of these. There is a whole round of analysis to determine the
causes of the X-generators. We had to remove static as well as dynamic
(timing) related hazards. We used TetraMAX extensively for DRC,
extraction and debug. This worked very well.
Once we had the design free of static X's we started ATPG & simulation.
We also cleaned up dynamic X's using timing anaylsis. Used PrimeTime
to do anaylsis in DBIST mode.
The DBIST logic and methodology did provide us with very high pattern
compression and some amount of test time reduction. It requires a lot
of debug effort to make sure one can determine cause of failures on
silicon. This is mainly due to the fact that the data out compression
is via a MISR mechanism which is great for compression but very tedious
for debug. The debug flow needs some amount of hand holding to get it
to run on the tester.
The DBIST architecture does boast of multiple CODEC's (compressor and
decompressor) on chip but there is no easy way to determine how many
one would need for a certain device. This might cause more or less
logic to be inserted and could become iterative. It is also limited in
speed of operation due to the way clocking and scan operate. This,
though, has been claimed by synopsys to be fixed in their newer rev.
Overall SocBIST is good for high volume, low cost devices but requires
some handling to get it to work."
- Amit Sanghani of Nvidia
"Synopsys' DW memory BIST is too limited to be useful. Why black box
the logic? Are they proud of their IP or ashamed of it? It also
bounds you to use only their VCS simulator. Mentor's MBIST architect
is more powerful. It has more March algorithms as well as let the user
generate his own. Synopsys only allows the user to select from 4
canned algorithms. However, Synopsys is free with the DW library
so I guess you get what you paid for."
- [ An Anon Engineer ]
"I wrote our own memBIST and scan connection tool. But our other group
uses Mentor and likes it after they got through the tool crashing and
huge run time problems."
- Ross Swanson of Flextronics
"SocBIST to me is clearly a smart approach to reduce test data volume,
test time and the complexity of handling very large designs.
Synopsys has to work to tie in all the different tools together but
once done they will have a powerful offering. Given the links to DC
the integration will be very smooth.
Additional features would be stronger links to Astro/PhysOpt,
automatic constraint generation for scan mode, scan reordering and
better links for clock tree implementations that take into account
test modes.
These are all difficult items but it appears Synopsys has the basics
in place."
- Gregg Shimokura of STMicroelectronics
"Mentor TestKompress vs. Synopsys SocBIST
Haven't had any experience in using TestKompress or SocBIST, but we've
had presentations in both. From what we can see TestKompress' ability
to handle Xs is a plus. With large designs, it's difficult to
eliminate all occurrences of Xs during testing."
- John York of ATI, Inc.
"LogicVision seems to be ahead of the group, although SocBIST and
TestKompress are pretty new products. Until we see some designs
successfully implement logic BIST using either one, it's going to be
difficult to say who's best. Here again Synopsys may have a edge,
even though they came to the game pretty late, because of the tight
link to synthesis. I guess time will tell us.
I want to add one thing that you forgot to mention. Memory BIST.
Synopsys is pretty much absent and what they offered in the past wasn't
very user friendly. It wasn't even part of the DFT tools suite. Here
LogicVision is clearly the winner so far."
- Amar Guettaf of Broadcom
|
|
