( SNUG 03 Item 7 ) ----------------------------------------------- [05/14/03]
Subject: Verisity Specman "e", Synopsys Vera, Forte RAVE
VERA'S STAGNATION: Last year, the Vera vs. Verisity battle was a dead heat;
anyone could win this game. Now, looking at the Dataquest numbers, it's
clear that Verisity Specman "e" has won the battle.
Dataquest FY 2000 Functional Test Simulator Market (in $ Millions)
Synopsys Vera ###### $12.0 (43%)
Verisity Specman 'e' ###### $12.0 (43%)
Forte/Chrono RAVE ## $3.6 (13%)
Total ############## $28.0
Dataquest FY 2001 Functional Test Simulator Market (in $ Millions)
Synopsys Vera ###### $12.5 (30%)
Verisity Specman 'e' ############ $24.2 (58%)
Forte/Chrono RAVE ### $4.6 (11%)
Total ##################### $41.8
But, judging from many of the user comments below, it might be a Pyrrhic
victory for the Verisity folks. That is, Aart's Superlog / System Verilog
push just might put both Vera and Verisity on the Endangered Species List.
"Specman has an edge over Synopsys in terms of technology. Once you
get over the language learning curve of e, Specman is more powerful,
flexible and resuable than Vera. We also like Specman's stand-alone
simulation mode to quickly check stimulus coverage and to do vector
filtering.
However, Synopsys has a much better business model and future road
map. Vera is virtually free with VCS. Direct C interface with VCS
also boosts its performance. System Verilog is more similar to Vera
than e. In case System Verilog picks up, it's easier to transition
from Vera than from e. OVA is another side benefit. Vera is cheaper,
too. I think any shortcoming of Vera can be fixed by Synopsys, but
not sure how Verisity can fix their business model and e's questionable
future fate."
- Wilson Chan of Qualcomm
"Is this the death knell for proprietary verification languages?"
- Matthew Henry of Agere Systems
"Both e and Vera are losing value with System Verilog being promoted,
especially if all of the EDA vendors get on the wagon and promote it
as a coherent language spec with none or small incremental costs to
the initial simulation tool purchase."
- Gregg Lahti of Microchip
"I used Specman on a project a couple of years ago. I really liked the
power of the language, but it was too slow and too hard to learn.
Designers who had no interested in learning a new environment/language
either stayed completely away or had to bite the bullet and try to
learn e. The learning curve was a step function. Superlog fixes that
problem, at least for those that already know Verilog. I haven't used
Vera on a project. I don't see how Verisity's business model can be
sustained when System Verilog becomes widely available."
- [ An Anon Engineer ]
"Vera lite would save tons of sim time (and we may use it in the short
term), but with the Superlog purchase, I think we will be headed in
that direction for the long term."
- Patrick Allen of Infiniswitch
"I hope both of Specman & Vera go the way of the Dodo bird. A complete
waste of design resources and capital budget."
- [ An Anon Engineer ]
"Both Vera & Specman e are losing. Both are doomed. As soon as System
Verilog is in place, nobody will pay extra for features which are
already in their primary design language."
- Dave Chapman of Goldmountain Consulting
"Both Vera & e are losers until synthesizable. You cannot run on an
emulator until synthesizable, and I beleive that emulators (such as
Paladium) are the wave of the future. Maybe System Verilog will
solve these problems."
- Arthur Nilson of Unisys
"Who cares! I believe eventually everybody goes to System Verilog."
- [ An Anon Engineer ]
"Neither Vera nor Verisity is winning. The majority of designers still
generate their test benches by hand."
- [ An Anon Engineer ]
"Vera and "e" offer similar capabilities. Vera wins in the learning
curve department. "e" has a lot of internal things going on that
just make it harder to learn. In my evaluation of "e" I'd write some
code that seemed perfectly logical. The Verisity AE (with 3 months
experience) could not tell me why it didn't work, and had to call home
to Engineering to get an answer. Also the "e" syntax is a little
strange.
Vera on the other hand seems like a logical cross between C++ and
Verilog. We had groups using Vera for verification. But "e" is also
viable. We would have used it if we were working with certain other
groups in the company."
- Tom Thatcher, ex-Agilent and looking
"I was exposed to Specman E when I was at AMCC, but never actively used
it. It seems like a better way to verify a design than using plain
Verilog. Don't know much about Vera. I'm fairly confused as to how
these languages fit into static & dynamic assertion-based verification
and any of the other new verification techniques out there."
- Tomoo Taguchi of Hewlett-Packard
"In interviewing many candidates, it seems the market is pretty much
50-50% divided between e and Vera."
- David Lau of PMC-Sierra
"We use Verisity-Specman and I am conviced it is a much better choice.
Synopsys now claims they can do better with new Vera, this may be true
but since all verification environment are now built in e, it's would
require too many efforts to switch."
- [ An Anon Engineer ]
"I think Vera is winning. More users. Easy to use."
- [ An Anon Engineer ]
"We did the compare and chose Specman about 3 years ago. I hear that
Vera is better now than it was then. Although I have concerns about
the language design, our folks have picked up Specman quickly and
made great use of it."
- Ken Sailor of PMC-Sierra
"Have not touched either Vera nor Specman."
- Bengt-Erik Embretsen of Zarlink Semiconductor
"Officially LSI is a Specman house, but not many people actually use it.
Many (myself) can't wait to jettison all traces of 'e'. So much
investment, with disappointing results. Our in-house C++ verification
environment or SystemC/TestBuilder is preferred."
- [ An Anon Engineer ]
"We use a local Agere Ottawa developed testbench suite, so we do not use
Vera or e. (We just hired a verification guy who loves e, so can you
say "let's re-design the whole testbench environment again?")"
- Bob Lawrence of Agere Systems
"I prefer Specman though I haven't fully learned it. I have barely
used Vera."
- [ An Anon Engineer ]
"We using Vera now."
- Rex Tung of InProComm
"Looks like Vera is winning at least from a standards point. I do not
know either language well enough to comment on it."
- [ An Anon Engineer ]
"Verisity is winning this. Verisity are really thinking about the
methodology and how to extract the best from the technology, and are
making this widely known. Why did Synopsys buy Qualis - it was at
least to fill the gap they had with their tool approach here. The fact
that they had to go with OpenVera rather than keeping it as a
proprietary tool/language would seem to be an admission that it wasn't
becoming as accepted as quickly as they would have liked."
- [ An Anon Engineer ]
"I think Vera is superior. We've used it to the fullest extent, and it
has paid off in terms of getting verification done much faster. We can
even build a basic test bench and add/enhance objects very easily. We
originally used Vera for the added control, but now the object oriented
approach is the key. We were never very impressed with Specman. Vera
was easier to use and easier to understand."
- Curtis Jones of Hewlett-Packard
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