( SNUG 03 Item 4 ) ----------------------------------------------- [05/14/03]
Subject: The Bigwig's Big Speech
OUT WITH THE OLD TO MAKE ROOM FOR THE NEW: This year, as usual, Aart gave
a keynote that was a sort of State of the Synopsys Technology Union address
that covered most everything Synopsys & Avanti touches. The take away that
users subtly got when Aart said that System Verilog was the wave of the
future was that this was the official Synopsys Death Certificate for both
VHDL and sometime later, SystemC.
"VHDL is dead. (Or maybe I should say it's been great for a long time,
and needs no further improvement.)
- Arthur Nilson of Unisys
"OK. The notion that VHDL is the new Latin and has about 5 years left
at Synopsys has gotten mixed reviews around our group. I've used VHDL
and Verilog and personally don't care which is used. System Verilog
looks better for simulation benches so if that forces us into Verilog
some of our group will be unhappy during the transition."
- Lance Flake of Maxtor
"I hope Aart keeps to his word on the System Verilog role-out. I just
want Formality to properly support it."
- [ An Anon Engineer ]
"Tuesday March 18
Keynote Address - Aart de Geus
Packed conference room even at this early hour. Aart doesn't look like
a very cheerful guy, but definitely he's better than Cadence's CEO.
So far nothing new in his address. Challenges for the future: timing
in deep submicron, and most importantly signal integrity and power
(big news...). He quickly moved into describing Synopsys backend tool,
Astro with the Milkyway database, stressing the "open database"
initiative. Well... they arrive 1 year late to Cadence initiative.
It's somehow pitiful that less than 1 year after acquiring Avanti,
Synopsys "entire" strategy depends on Avanti's Astro... I guess their
own tools were not very good.
Same in test. TetraMAX is their best tool. He, just a few minutes ago
they were trashing TetraMAX in favor of their own Test Compiler line
of products. I guess customers stayed with TetraMAX which, by they
way, was acquired by Synopsys a couple of years ago.
They just bought another company that deals with masks. This will help
them to add OPC (optical proximity correction) and PSM (phase shift
mask) technologies to create layout masks.
Big push for System Verilog as the next big thing to integrate design
and test. Yeah, the will drop Vera. As usual, big fuss about Vera last
year, big fuss about System Verilog this year. Will they ever make
their mind up (or more important, will they ever think and debug
before they offer new stuff?. A bit of industry collaboration between
big players would also help...). I wonder if all this smart guys did
ever think about the needs of large designs: run as many tests as
possible. With their new languages, heavily overloaded by fancy new
features, and lousy software developers, we'll be able to run 10 test
in the same time we used to run 1000 before.
And there he goes with all this assertion stuff.
He talked a bit more about Synopsys as a company, revenue, and some
more stuff. One of the most interesting things he said is that
Synopsys invests 25 ~ 30% in R&D. Wow! Looking at the quality of their
tools they either produce lots of stuff we don't know about, or they
need lots of engineers to produce the low quality they deliver...
Q&A session
Q. Design GAP between productivity and design tools. Companies have to
make decisions long term on technology. Synopsys tools don't keep up
with technology. How companies should plan?
A. They have too many tools, and it's very difficult to plan what's
needed in short/long term.
Q. License costs is forcing people out
A. Business is in the license. Aart points out that making chips is
now more expensive, so we have to live with higher license prices.
Q. DesignCon said that VHDL is going to grow. Synopsys says VHDL will
not grow. Comments?
A. Synopsys will support VHDL at a basic level, but that's it.
Q. Synopsys tools bugs. We don't feel like using Synopsys because of
the poor quality of the tools.
A. Tools have bugs. We are doing as much as we can to fix them.
Q. Can we go with Synopsys backend tools, even though it's in the
middle a merge with Avanti?
A. Sure. We will produce a good set of tools this year
Personally I felt highly dissatisfied with Aart's answers to all the
questions. It gave me the feeling that Synopsys is a not well
organized/managed company, that they have no QA, and that they have no
plans to have QA in the future.
- Santiago Fernandez-Gomez of Pixim, Inc.
"Aart's keynote speech is always the highlight of SNUG, and this year
was no exception. In the questions at the end the dominant concern
seemed to be the high cost of tools, which is becoming a barrier to
entry. I think Aart partially answered that concern."
- Tom Thatcher, ex-Agilent and looking
"Really enjoyed Aart's keynote address - Cadence appears to be going
whole hog SystemC. Do we have the verilog/VHDL thing all over again?"
- Ken Sailor of PMC-Sierra
"The guy can really talk well."
- Dave Chapman of Goldmountain Consulting
"Synopsys vs. Cadence
In general Synopsys tools are a much more of Class Act than Cadence.
We can solve 95% of our issues on SolvNet where as we don't have a
prayer on Sourcelink. Cadence does not belive in describing the
"error" and "warnings" their tools generate. Nor do they care about
explaining the methodology behind their tools. We were actually told
regarding their SI tool to "not to be so worried about understanding
the results and reports, but just implement the recommended fixes like
all other users do". And the issue of managing releases/versions is
a nightmare with a custom release almost weekly for various customers.
We have called Cadence AEs only to find out that our 4 week old release
is already 4 versions behind.
Cadence's tools drive like a Ford, while Synopsys's tools drive like
a Lexus. You pay more, but the total cost of ownership is not higher."
- [ An Anon Engineer ]
"Everybody knows VHDL is going down. Aart just set a date for it to
retire."
- [ An Anon Engineer ]
"I thought Aart's talk was, as usual, great. (I've known Aart for
20 years.) But, like many people, I was a bit surprised to hear that
language verbosity was the biggest problem with an HDL and that
System Verilog would be the future HDL -- rather than an extention
to Verilog."
- Bob Lisanke of Nontrivial Systems Corp.
"As always Aart had a great speech full of interesting factoids. It's
good to see a CEO provide a vision of how to advance and grow the
company during this wicked crapstorm of an economy and provide a
technological future that looks pretty bright."
- Gregg Lahti of Microchip
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