( SNUG 02 Item 11 ) -------------------------------------------- [ 5/15/02 ]
Subject: Design Compiler, Ambit-RTL, Get2chips, Synplicity ASIC, Incentia
ATTACK OF THE CLONES: Not much has changed in the ASIC synthesis market.
Synopsys Design Compiler still easily dominates against 4 rivals.
Dataquest FY 2000 ASIC Synthesis Market (in $ Millions)
Synopsys ############################### $154.7 (87%)
Cadence/Ambit #### $18.7 (10%)
others # $5.2 (3%)
Cadence's Ambit BuildGates is the distant 2nd place contender to DC, but it
has all the problems & support of a low importance tool inside the Cadence
empire. As far as I can tell, it's just a basic synthesis tool. I'll wish
you luck if you're using Ambit on a large design with multiple unrelated
gated clocking and scan issues. You'll need it.
Get2chip.com may not have Ambit's 10% market share (yet), but they seem to
be focusing on building better RTL synthesis. You'll get better support
from them because it's their cash cow; but this may disappear if the rumors
about Cadence buying Get2chip.com are true.
Despite the media hoopla (ESNUG 393 #3), Synplicity's Synplify ASIC appears
to be a greener version of Ambit. Over the past 12 months, Synplicity has
reported to the Wall St. analysts in their quarterly conference calls that
their ASIC synthesis tool has a grand total of 12 customers. That's still
beta country as far as I'm concerned.
And Incentia from Taiwan? I'll let Nvidia's Oren Rubinstein describe
them: "Ambit had potential before being acquired by Cadence. Synplicity
never got past the FPGAs (not seriously, anyway). I tried Get2chip about
a year and a half ago. It wasn't there yet, but I don't know about its
current state. What is Incentia?"
Customers do like the idea of having viable alternatives to Design Compiler.
But users have too many scripts and too much personal know-how invested in
Design Compiler. It's just not worth it to them to risk *their* chips (or
*their* careers) on any of these alternatives.
"Price isn't everything, or we'd all be driving Yugos."
- Gregg Lahti of Intel (ESNUG 333 #2)
"Competition is good, even if I'm not using the competition's tools."
- Neel Das of Corrent Corp.
"DC works. Everybody speaks it. I'm stick'n to it until somebody
else has 50% market share in ASIC Synthesis."
- Kevin Hubbard of Siemens
"We have both Synopsys and Ambit licenses. However Ambit does not run
on Linux. Synopsys is consuming a lot of MIPS compared to Ambit but
a fast Pentium4 machine with Linux can makeup for some of this.
Therefore Synopsys on Linux is our choice. We also use Power Compiler
to insert clock gates which we have not tried with Ambit."
- Karl Kaiser of Resonext
"We did very careful detailed comparison between Ambit and Synopsys
synthesizers and we got to the conclusion that they give identical
performance, but Ambit cost 1/5 of Synopsys and have also built-in
scan insertion mode with no extra charge. So Ambit is our RTL
synthesis tool."
- Gideon Paul of TeraChip
"Never used ACS (Automatic Chip Synthesis). Can't we just have a
stable flow for a few years? (kidding) Synopsys is still the best.
Investment in scripts and knowledge keep it that way whether it is or
not. And it's 'Design Vision' now, DC is passe."
- Brent Lawson of Texas Instruments
"All of my customers are nowing looking into new synthesis tools. They
use Synopsys DC as the reference, and then take the best results from
Incentia or Get2chips, both which are producing good results
with faster runtimes."
- Tom Moxon of Moxon Design
"SNUG'02 Paper: RTL Coding and Optimization Guide for use with
Design Compiler, Jack Markshall, Tera Systems
This paper focused on the impact of RTL styles on synthesized logic,
specifically when using Design Compiler for synthesis. This paper was
so full of value, it should be referred to before starting any new
project, and probably several times during a design cycle. Suggestions
are made for pre-coding checklists, the importance of paying attention
to DC messages, rewards of preparation. The paper on the CD, as well
as in the manual, is a bit mixed up, with the general slides listed
first, followed by appendix slides which had the real meat. Rather
than just parrot the slides, I would just make a recommendation that
this be read and used as part of our design cycle."
- Eric Mitchell of Cypress Semiconductor
"We like DC and have yet to see overall incentive to change. We used
ACS for our last chip, liked it, and plan to use it again on our
current chip."
- Jeff Waite of Netergy Microelectronics
"About ACS: I think its good but costly. Why? It's because most of my
jobs per block, takes on an average of 10 hrs. My design is over 10 M
equivalent gates, divided in approx 30 blocks. Each block is thus
300k+ gates. Using ACS means I need to give-up on 1 license which will
manage all the jobs. I have my Perl scripts which manages the jobs. A
separate Perl script summarizes the report on all the blocks, and also
tells me if the job has not finished.
It will be useful if the main process can manage the other jobs as well
as synthesize a block or few in spare time."
- Hemant Kumar of Morphics
"The conservative part of me says: keep what works, what you've had
years of experience using. Design Compiler is mature, has been for
years, and 'everybody' uses it. We have zillions of scripts. Don't
stir up a hornet's nest & get stung.
The other part of me says: man, they charage a lot of money, and the
tool, despite what they say, still doesn't do a great job of compiling
complex designs top-down. I'd love to be able to use Get2Chip's tool
(we've played with it some). They seem to be taking the right approach
to the synthesis problem for BIG designs. And as a small company, they
seem willing and eager to work with you on both technical and business
side of things. Haven't tried Ambit or others."
- an anon engineer
"Design Compiler is still in the lead. I would like to see someone
compete, but have yet to experience this."
- Scott Vincelette of Flarion
"DC seems to work fine for us as a synthesis engine, although I can't
say we've ever considered alternatives. I won't say its the best tool
for the money. The guys at Cadence would probably pay us at Philips
to publicly endorse Ambit, but then other people have to deal with
that problem not me. I just want my design to work and if we have to
pay insanely high maintenance/license fees to Synopsys Inc for it, so
be it. But I don't have to be happy about it."
- an anon engineer
"We are a long time users of Design Compiler, and it wasn't even
considered to try anything else. However, through an acquisition,
we got hold of few Ambit licenses. Couple of months ago, we were in
a situation in which we were short of DC licenses because a few
projects entered synthesis at the same time. I suggested to one of
the project managers to give Ambit a try and it was a success. After
a relatively short time, the scripts were converted, and with good
support from Cadence, we were able to run the entire project in Ambit.
The results were comparable to DC (some blocks better, some worse).
For the final runs, we will probably switch back to DC, but as I see
it, we will start using Ambit more and more in future designs."
- Nir Sever of Zoran
"We have been doing some comparisons between Design Compiler and Ambit
and the results are slightly better for Synopsys than for Cadence. The
big advantage on Ambit is the time it takes to synthesize the designs.
Since we prefer results over a short synthesis time, we will continue
to use Design Compiler.
Regarding ACS, it reduces the scripting time but the results appear to
be slightly worst. Nothing is free."
- an anon engineer
"Although ACS is nice it is an additional $ which 99% of my client base
have never needed. In fact with the improvements to DC with simple
compile mode; I get acceptable results that I can then do a "compile
-inplace" on after the first P&R run. Many of my designs are big but
not fast!
I think Synplicity ASIC will fall flat; the CTO does know his stuff,
but I haven't met an ASIC design which can use a pushbutton flow. You
didn't mention Exemplar, they have had an ASIC flow for years!
Get2Chips and Incentia have interesting stories to tell, we'll have to
see how they fare. Given the fact that they have completely re-written
the database from scratch they may have something!
Cadence is still pushing Synopsys, which is good, and the little
startups are just beginning to address issues that Synopsys may not
have identified. The capacity vs. speed issue being a big one. It was
great when DC allowed us to grow from 5K blocks to 25K blocks to 100K
blocks in a couple of releases. We still have capacity issues which
the little guys are solving, new database without any legacy stuff,
which Synopsys can't match."
- Tom Tessier of t2design
"As mainstreamers we expect to stick with Design Compiler and will
probably migrate to PhysOpt eventually."
- Scott Campbell of Motorola
"I tried Ambit Buildgates about a couple of years back. Based on what
I've seen, I can tell you that its not worth wasting your time on.
Synopsys was way ahead. It really pains me to see these startups who
make tall claims about their tools when their underlying technology is
not vastly different from Synopsys. They do not publish any technical
details about their technology, but use terms like 'pin-based timing
analysis' and 'behaviour extracting synthesis' to justify why their
tools are better. As if I'm supposed to know what 'pin-based timing
analysis' is all about.
When we benchmarked Ambit, we began to discover so many limitations.
It's VHDL support sucked big time. There were no DesignWare quality
components to use. When we changed our RTL so that it could be read
into Ambit, we found that there were errors in the generated netlist.
So we decided to give up.
Basically, companies like Cadence and Mentor were built on efficient
schematic and layout generation. They probably thought that synthesis
will never be the preferred way of implementing designs - and that's
why they're struggling to catch up.
I tried ACS, too. It's remarkable how Synopsys can keep thinking of
such things. For designs with simple clocking schemes, etc., ACS
compiles are the best. It takes us hardly any time to get a netlist.
I am waiting for something that will couple ACS with PhysOpt, which is
now becoming part of our synthesis flow."
- an anon engineer
"Design Compiler rules. Ambit had potential before being acquired by
Cadence. Synplicity never got past the FPGAs (not seriously, anyway).
I tried Get2chip about a year and a half ago. It wasn't there yet,
but I don't know about its current state. What is Incentia?
As for ACS, it doesn't fit in our current methodology, but it's a good
idea, so maybe I'll try it one of these days."
- Oren Rubinstein of Nvidia
"If Synopsys gets some major competition in the ASIC synthesis area,
I will jump on the band wagon. Synopsys's price increase from two
years ago is still stuck in my throat. ACS is something which has
been in Exemplar and Synplicity for years for FPGAs, and Synopsys
is just figuring it out now for ASICs."
- David Bishop of Kodak
"We only use Design Compiler and are not very knowledgeable about the
other options, though I'm quite pleased that others are giving Synopsys
a challenge. I don't like having just one big gorilla in the market."
- Curt Beckmann of Rhapsody Networks
"I'm only using Synopsys Design Compiler currently. I've used
Synplicity for FPGA prototyping, and there were some oddities that
needed sorting out before everything would compile. I'm a big
fan now of DC."
- Eric Mitchell of Cypress Semiconductor
"We are using Design Compiler exclusively. We are not using Automated
Chip Synthesis (ACS). Synopsys tech support beats Cadence hands down
so we are sticking w/ DC. Haven't tried any of the smaller players.
Libary support would be an issue for other tools outside of DC."
- an anon engineer
"Due to the lack of competition, Design Compiler hasn't make much
improvement for the past year. Synopsys is undoubtfully the biggest
guy in the landscape. The trend among synthesis users is to use 'ACS'
(Automatic Chip Synthesis). For large chips this is the way to go.
Though there were no papers for ACS this year, the tutorial session
did spark lots of discussions about this methodology.
DC Ultra license won't be integrated into DC in the near future.
Synopsys still wants to make the most $$ out of it."
- Andrew Cheng of Cisco
"Synthesis Highlights in DC 2002.05:
+ Support for ILMs in synthesis
+ Improved Verilog reader can distinguish between netlist and RTL
+ Better handling of bidirectional ports
+ Fix DC-TCL memory requirements
+ Many other minor improvements
DC-Ultra Enhancements:
+ Better FSM/datapath optimization,
+ compile_ultra command reduces variables that need to be set.
Advanced Chip Synthesis (ACS) is a tool in DC to:
+ Budget lower level partitions from top-level constraints
+ Provides Top-level synthesis commands
+ Manages parallel synthesis jobs on multiple CPUs
Q: How does the ACS parallel job function compare to Makefiles?"
- Kent Ng of Microsoft/XBox
"Synthesis Highlights in DC 2002.05:
- significant runtime enhancements
- can create on-the-fly Interface Logic Models (ILMs) to improve
capacity, also for PhysOpt (see Physical Compiler Intro Tutorial
for more on this topic) and for DFT-Compiler
- read_verilog & read_file now merged into read -f verilog (yeah!)
- better bidir ports w/ (timing_disable_internal_inout_net_arcs)
- ideal_network command to propagate ideal nets (note that the
latency and transition times can be set manually on these nets)
- improvements in TCL performance, Design-Vision and FSM-Compiler
- DC-Ultra now accessible through compile_ultra command
Plus a set of scripts to automate the ACS flow.
- an anon engineer
"Of course, DC still dominant the market, but the capacilty has to be
improved. ACS for me, it looks like a work-around."
- Hui Fu of Infineon
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