( SNUG 02 Item 3 ) --------------------------------------------- [ 5/15/02 ]

Subject: Exactly Who Came To SNUG'02?

A MINI-CENSUS: This data comes from the customer survey taken at the SNUG'02
meeting itself.  A total of 269 out of the 451 SNUG'02 attendees responded.

Here's the stats on the types of designs these engineers are creating:

          Standard Cell / SoC  ######################################## 79%
                  Full Custom  ##### 11%
                   Gate Array  ## 5%
                    FPGA/CPLD  ## 4%
                        Other  # 2%
 
The speed, size, and process of the chips they're designing:

                  1 -  99 MHz  ###### 13%
                100 - 199 MHz  ############ 25%
                200 - 299 Mhz  ############## 27 %
                300 - 499 MHz  ############ 23%
                   500 + Mhz   ###### 12 %

               1 - 300 Kgates  ######### 17%
             301 - 500 Kgates  ###### 12%
             501 - 999 Kgates  ## 4%
                 1     Mgates  ######## 16%
           1.001 - 2   Mgates  ########## 19%
           2.001 - 5   Mgates  ######### 18%
                 5+    Mgates  ####### 14%

            0.25 um or higher  # 3%
                      0.25 um  ### 7%
                      0.18 um  ######################## 48%
                      0.15 um  ##### 10%
                      0.13 um  ############# 26%
                      0.11 um  # 3%
                      0.10 um  1%
                below 0.15 um  # 2%

Ckeck out last year's stats in SNUG 01 #3 and you'll be surprized to see
how dramatically things have changed in one year -- especially in design
gate counts and fab processes being used.  Last year only 36% of designs
were 1 million gates or more.  Now 67% are!  Last year 73% of designs were
at or below 0.18 um.  Now 90% are.

Their P&R design flow:

  Hand-off P&R To ASIC Vendor  ############### 29%

            We Use Avanti P&R  ################# 33%
           We Use Cadence P&R  ############ 24%
             We Use Magma P&R  # 3%
  We Use Our Own In-House P&R  ## 5%
                  "other" P&R  ## 6%

Again, much has changed in 12 short months.  Last year, 59% of designers
handed off P&R to their ASIC vendor; this year only 29% are.  Also 18%
used Avanti P&R and 16% used Cadence P&R.  This year it's 33% Avanti,
24% Cadence, and 3% Magma for customer-owned P&R tools.


And the fabs they're designing for:

         In-House Company Fab  ################## 35%

                         TSMC  ########################## 52%
                          UMC  ############### 29%
                          IBM  ######### 17%
                          LSI  ######### 17%
                       Xilinx  ###### 13%
            Texas Instruments  ##### 10%
                       Altera  ### 6%
                      Philips  ## 5%
                    Chartered  ## 5%

           STMicroelectronics  
         NEC, Fujitsu, Lucent
          Toshiba, Mitsubishi  # 3% or less

While these numbers are generally the same as last year's, this year TSMC
and UMC jumped dramatically.  Last year (2001) they were:

                         TSMC  ############### 31%
                          UMC  ##### 10%

Which explains why all the EDA vendors are going out of their way to say
that they work with TSMC in their press releases.

So, in a nutshell, SNUG'02 was a conference of high-end chip designers.


    "The one thing I appreciated at SNUG was the poster session.  I think it
     is a really valuable part of the conference -- both for the presenters
     as well as the audience."
 
         - C.V. Krishna of Case Western Reserve University


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