( SNUG 01 Item 20 ) -------------------------------------------- [ 3/28/01 ]
Subject: Synopsys "PrimeTime" -- Sitting Pretty
QUIET UPSETS: PrimeTime has been the source of some quiet upsets in the
Synopsys user community. First, this year instead of some DC (or possibly
PhysOpt) paper winning the SNUG'01 Best Paper, the winner was a paper by
Paul Zimmer of Cisco on how to handle tricky timing analysis situations
in PrimeTime. In ESNUG recently there have been vociferous debates on real
vs. false monotonic PrimeTime libraries. (See ESNUG 366 #6 & back.) And
the only solid technology leak Aart made this year involved Signal Integrity
comming to PrimeTime.
"I do chip Timing Sign-off with ...
Static tools only ############################################# 91%
Dynamic tools only ############# 26%
Both Static & Dynamic ######## 17%
"6) Signal Integrity -- Here, Aart could only hint at a solution
'soon to come'. This is probably tied in with the detail
router solution to be integrated into Physical Compiler.
Everybody at Synopsys is being notably cautious about
revealing any sort of release date for this stuff. I suspect
it's because they require a major update to their internal
timing engine in order to handle detail routing properly
(ie, integrate the PrimeTime engine into Physical Compiler.)"
- Rich Conlin of Paradigm Works
"3) New cross-talk analysis will force us away from SDF.
Synopsys' proposed method of dealing with cross-talk issues is to make
PrimeTime aware of the effect of cross-talk on timing. What this
implies for us is a move AWAY FROM SDF, since delays can no longer be
thought of as independent of timing constraints (the delay on a net
depends on the *timing* of nets switching nearby). To make use of
Synopsys' cross-talk analysis capability, we will have to move to
something like SPEF files and depend on PrimeTime models to calculate
the timing.
This raises the obvious question of timing accuracy. There was an
excellent paper from LSI on the problems that stem from not having
any industry standard for timing calculation."
- Paul Zimmer of Cisco Systems
"PrimeTime Update
This talk was an extremely detailed talk on the 2001 updates in
PrimeTime. The main improvement is a brand new reduction algorithm
for reading in detailed parasitics, called the "Arnoldi Reduced
Order Model". This model reduces the driving cell into an ideal
voltage source with a series resistance and parallel capacitance.
The R and C values are chosen to give the same characteristic as
the full backannotated RC network for each net. If you read
ESNUG 366 #6, this algorithm has recently been the source of some
heated discussion due to the fact that it requires library delay
values to increase monotonically with increasing capacitive load
(RC-004 error messages). The talk went into quite a bit of detail
on the algorithm.
The talk also introduced a new extracted timing model for hierarchical
timing analysis called the Interface Logic Model (ILM). This is
different from a STAMP model in that the ILM simply removes all the
internal register-to-register paths within the block; all interface
logic (and therefore all the backannotated parasitics for the
interface logic) is retained. It seemed a resonable solution to the
limitations of the STAMP models you had to use in the past."
- Rich Conlin of Paradigm Works
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