( SNUG 01 Item 3 ) --------------------------------------------- [ 3/28/01 ]
Subject: Exactly Who Came To SNUG'01?
DESIGN, DESIGN, DESIGN!: This data comes from the customer survey taken
at the SNUG'01 meeting itself. A total of 321 out of the 485 SNUG'01
attendees responded to this survey.
Here's the stats on who came:
Design Engineer ############################### 63%
Design Eng. Mgr. #### 8%
CAD Engineer ########## 20%
CAD Eng. Mgr. ### 6%
Academic # 2%
Other ## 4%
The types of designs these engineers are creating:
Standard Cell / Gate Array ############################## 60%
System-On-A-Chip ############### 31%
Full Custom ####### 14%
FPGA/CPLD #### 9%
Other ## 5%
The speed, size, and process of the chips they're designing:
1 - 99 MHz ############ 23%
100 - 199 MHz ################ 33%
200 + MHz ###################### 44%
1 - 100 Kgates ######## 17%
101 - 500 Kgates ########## 21%
501 -1000 Kgates ############# 26%
1 Million + ################## 36%
0.35 um or higher ### 6%
0.25 um ########## 21%
0.18 um ######################### 49%
below 0.18 um ########### 23%
Their design flow (COT means they're doing their own place & route):
ASIC design flow ############################## 59%
COT Cadence P&R ######## 16%
COT Avanti P&R ######### 18%
COT in-house P&R ## 4%
COT "other" P&R # 3%
And the fabs and/or FPGAs they're designing:
In-House Company Fab ################## 38%
TSMC ################ 31%
IBM ######## 16%
LSI ######### 18%
Texas Instruments ###### 12%
UMC ##### 10%
Lucent ## 4%
Toshiba ## 5%
STMicroelectronics
NEC, Fujitsu, Charter,
Mitsubishi # 3% or less
Xilinx ################ 33%
Altera ############ 23%
So, in a nutshell, SNUG'01 was a conference of high-end chip designers.
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