( SNUG 00 Item 18 ) -------------------------------------------- [ 4/05/00 ]
THE BIRDS & THE BEES: Currently, to manage the funky effects of hanging
out around 0.25 um, chip designers use Design Compiler in conjunction with
Wire Load Models. They're also using a class of tools which guesstimate
physical effects (within 15 percent or so) that are best thought of as
"planners". Their user stats:
Avanti Planet-RTL ######## 17%
Synopsys Chip Architect # 3%
Synopsys FlexRoute 1%
Once you're past the physical effects planning stage, there's another class
of tools that manages physical effects via post-synthesis optimizations.
Their SNUG'00 tool survey stats:
Synopsys Floorplan Manager ########## 21%
Avanti Saturn ###### 12%
Cadence Phys Design Planner ## 5%
Cadence PBopt should also be included here for completeness even though it
wasn't in the survey. Anyway, the big problem is these Wire Load Model
tools/approaches only work so-so, but they're as good as it gets for now.
Also, everything gets much worst the deeper below 0.25 um you get. This
is where the new class of RTL-to-GDS-II physical synthesis tools come in.
Their SNUG'00 user survey stats:
Cadence Ambit PKS ## 5%
Synopsys PhysOpt # 3%
Magma BlastFusion 1%
And this is where John Cooley steps in for a nice little talk on the Facts
Of Life In The EDA World...
First off, remember that +/- 6 percent margin of error I talked about for
this SNUG'00 user survey data? It applies here. Basically, the big EDA
companies are in the fight of their lives as far as future business is
concerned. Because physical synthesis entails going from RTL-to-GDS-II,
whoever owns this market will be obscenely successful; whoever misses
it will be have all the business and respect that ViewLogic gets. (One
motto on the ViewLogic web site last year was "Believe In Reincarnation".
And, no, I'm not making this up.)
This being said, let's say you're a Magma or a Cadence and you don't have a
working physical synthesis tool yet. You spread FUD (Fear, Uncertainty,
and Dis-information) to buy time for your developers to get your own bloody
tool working and to stall customers from buying a rival's working physical
synthesis tool. If you're Synopsys and you just happen to be lucky enough
to have a mostly functional physical synthesis tool, you try to do your
best to prove to customers it does work despite the FUD being blasted your
way -plus- you generate your own anti-Cadence and anti-Magma FUD, too. If
you're Avanti and don't even have a physical synthesis tool, you promote
your Saturn netlist optimizer like crazy and pooh-pooh all RTL-To-GDSII
tools. And with FUD, it gets worst. EDA employees don't just work for
salary any more; they all wanna get rich off of company stock options just
like their buddies in the .com companies. So they're all using FUD to
trick that EDA analyst at Goldman-Sachs into upgrading her eval of their
individual stocks, too!
"Hey, John, these EDA company press announcements have quotes from customer
VPs in them; there must be something good going on for the customer VPs to
be speaking up.", you reply. And my answer is one word: MONEY. When was
the last time you saw a VP design a chip? VPs don't design anything! VPs
are corporate politicians. Follow the money. Customer VPs give cheery,
sometimes-outright-lying quotes because they get a serious price cut or
some other behind-the-scenes favor from the benefiting EDA vendor. Why do
you think you're seeing "Success Stories" from ASIC Alliance on *both* the
Cadence and the Avanti web sites? Why do you see nVidia on the Avanti and
Synopsys press releases? Why do you see ARM, Ltd. (every EDA company's PR
whore) promoting every EDA company's software everywhere? Why do you see
Fujitsu supporting both Ambit in the Cadence press releases and BlastFusion
in the Magma press releases?
For a detailed example, let's look at the recent hunk of FUD where Cadence
is repackaging PKS and trying to say it's "new" and "improved" with their
SP&R press announcement from last week. In it you have Jayan Ramankutty,
the VP of engineering at EmpowerTel saying:
"With PKS, we eliminated design iterations and got higher-performance
results in a much shorter time. Adding routing to PKS and PKS to
Silicon Ensemble will allow us to achieve correlation across tools
and continue meeting our aggressive performance goals."
Do some digging and you'll find Jayan Ramankutty was the same VP at Lara
Technology in the Ambit press announcement a year earlier. Do some more
digging and you find that EmpowerTEL and Lara Tech are the same company
(they're just about to split) and they have 12 Cadence Verilog licenses,
5 Ambit licenses, 1 PKS license, and 1 complete Cadence Silicon Ensemble
suit -- roughly about $1 million worth of software. Ramankutty's quote
vaguely implies they used PKS in a big tape-out. (I'm sure that's what
the Cadence sales force is saying to the customers and Wall Street.) It
turns out that, yes, this is the first known PKS tape-out I've found,
but PKS was only used on 50 kgates of MIPS core buried inside a 130 Mhz,
2.5 million gate design that had a lot of RAM. The role of PKS in this
design at EmpowerTEL was trivial -- yet the Cadence press release was
purposely written to *imply* much more. Classic FUD.
And they all (Synopsys, Mentor, Avanti, Cadence, Magma, Monterey, etc.,
etc., ...) do it! Don't trust any of them, I say. Here's my known
list of physical synthesis tape-outs as of April 5th.
Cadence PKS
Design Size Clock Company Location Designer Tape-Out
--------------------------------------------------------------------
50 kgate MIPS 130 EmpowerTEL San Jose, Can't Say Apr./00
core in 2.5 Mhz CA
million gate
design
testing PKS Toshiba San Jose, unknown none
on 200 kgates CA
dumped PKS Micron Can't Say Can't Say none
testing PKS Agilent Corvalis, Jay none
Oregon McDougal
dumped PKS Agilent Colorado Can't Say none
Magma BlastFusion
Design Size Clock Company Location Designer Tape-Out
-------------------------------------------------------------------
testing around 3-D Labs England unknown none
BlastFusion 200 Mhz
testing unknown SUN Calif. unknown none
BlastFusion Microsystems
testing unknown Texas Texas unknown none
BlastFusion Instruments
testing unknown Fujitsu Calif. unknown none
BlastFusion
Synopsys PhysOpt
Design Size Clock Company Location Designer Tape-Out
--------------------------------------------------------------------
5+ million > 180 nVidia Santa Clara, Joe Nov./99
gates Mhz CA Grecco
3+ million > 180 Matrox Montreal, David Nov./99
gates Mhz Canada Romanauskas
135 kgates unknown STMicro Europe Can't Say Dec./99
300 kgates ~150 STMicro Europe Can't Say Mar./00
0.18 um Mhz
8+ million > 300 SGI/Cray Chippewa Roger Apr./00
gates Mhz Falls, WI Bethard
1.2 million 66 STMicro Agrate, Ezio Apr./00
gates Mhz Italy Pacileo
DSP unknown Texas unknown unknown Apr./00
unknown Instruments
I can't say how I know that TI has taped-out a PhysOpt design, but it did
come from a historically reliable source. When I asked Synopsys about
this TI PhysOpt tape-out, they stonewalled with me with "We can't say that
they have. We can't say if they haven't."
So, as of April 5th, this makes: for PhysOpt, 6 (possibly 7) tape-outs;
for PKS, 1 small tape-out; and 0 tape-outs for Magma.
"P.S. I still stand by my original argument: this physical synthesis
crap isn't showing drop-dead results against the tuned "DC w/ timing-
driven placement" flows I have today. Why bother with them???"
- [ Tony, the Tiger ] from ESNUG 348 #3
"My local layout people had a real hoot over the slides in the Physical
Synthesis tutorial. Especially the slides on multi-pin bus routing
(crosstalk central) and the clock balancing cell (signal disintegrity).
Can't wait to try it! (sarcasm)"
- Brian Logsdon of Philips Semiconductors
"There was only one paper from Sam Appleton from SGI that was very
good. He actually showed die photos of before, and after their new
methodology. He achieved some impressive results with FlexRoute.
We all know that by intelligently placing the block pins we can get
the job done. The problem is how to you manage the pin placement
complexity. It was nice to see that Synopsys FlexRoute will do the
job. Now if I can convince my clients to pony up the necessary funds."
- an anon engineer
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