( SNUG 00 Item 17 ) -------------------------------------------- [ 4/05/00 ]
TRUSTING THEIR MOTIVE(S) When Synopsys bought ViewLogic a few years back,
they effectively bought the entire Static Timing Analysis (STA) market
because, at the time, ViewLogic owned the best and most popular STA tool
around: MOTIVE. Since then, Synopsys replaced MOTIVE with its own STA
tool, PrimeTime. It's funny how that paid off for Synopsys now:
I sign-off with Static
Timing Analysis (Only) ################################ 65%
I sign-off with both
Static & Dynamic Analysis ########## 21%
I sign-off with Dynamic
Timing Analysis (Only) ####### 14%
Also from the tool stats:
Synopsys PrimeTime ############################# 58%
Mentor SST Velocity 1%
Cadence's Pearl STA tool wasn't on the survey. Dataquest's 1998 market
share numbers gave Synopsys PrimeTime 74.1 percent, Cadence Pearl 22.6
percent, and Mentor SST Velocity 2.7 percent. Good acquisition.
"Strangely enough, it looks like it's a race between Synopsys and
Mentor in the static timing analysis market because Cadence is
de-emphasizing Pearl in favor of the Ambit static timing analysis
engine. Ambit STA is not a stand alone product yet, so it's not
in the numbers."
- Gary Smith, Dataquest EDA Analyst
"The second author, London Jin of Toshiba, presented a litany of issues
and pet peeves associated with static timing analysis using PrimeTime.
The first problem the author had was unknown clock networks which
resulted from "black box" cells in his clock tree. Primetime cannot
successfully propagate clocks through cells that are modeled as a
"block box". The "transitive_fanout -clock_tree" command was used to
uncover these unknown clock networks. The second problem Jin had was
untested timing checks. The "report_analysis_coverage" command was
used to uncover untested timing checks. Jin also suggested the use of
the "derive_clocks" command to extract and analyze clock networks
within a design. I'm glad I sat in on his presentation."
- an anon engineer
"Day 3: PrimeTime Special Topics (Tutorial Session)
This two-part tutorial first dealt with setting timing constraints and
then static timing models. The first part of the tutorial didn't
introduce any revolutionary information that wasn't already is use
within our group, with the exception of On-Chip variation. On-Chip
variation is the capability of Primetime to account for delay variations
due the PVT changes across the die. When using on-chip variation, a
"clock reconvergence adjustment" is used by Primetime to account for
cells common between the clock and data paths. It is assumed that a
single cell cannot have two delays. The second part of this tutorial
presented three types of static timing models that are available with
PrimeTime: Stamp Timing Models, Extracted Timing Models, and Quick
Timing Models. Stamp Timing Models are primarily used by ASIC vendors
to characterize such things as memory cells.
Extracted Timing Models are very interesting and could be very useful
to reduce the run-time of static timing analysis. A timing model can
be "extracted" automatically from a design instance and used for
subsequent timing analysis. Since the extracted timing model only
contains the information necessary to model timing at the boundary of
the design module, it reduces run-time.
Quick Timing Models are also interesting as they can be used to describe
the timing of a design module where no netlist is available. This can
be useful during hierarchical design to best describe the timing
characteristics of a design not yet complete. How to extract a Timing
Model and generate a Quick Timing Model were both presented."
- an anon engineer
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