( SNUG 00 Item 13 ) -------------------------------------------- [ 4/05/00 ]
FROM C TO SHINING C: So far there are at least 4 major initiatives to make
a C Standard for HW design. C-Level has one from EASICS; SpecC is from
U.C. Irvine & Toshiba; Synopsys has System C; and CynApps has CynLibs.
Each is backed by an endless list of companies and Motorola appears to be
backing them all! Here are some of the details of system C. It is class
libraries for C++ that allow hardware to be modeled. It uses standard
C/C++ development along with the class libraries, and C/C++ source to
produce an executable which is your simulation. That simulation can run
on any platform. The key classes are:
Concurrency - processes (sync and async)
Communication - signal, channels
Notion of time - multiple clocks with arbitrary phase
Reactivity - watching for events
HW data types - bit vectors, arbitrary precision integers
Simulation support - debug support, VCD files
Here is an example for an adder that adds a + b then registers the output
to register c in both Synopsys SystemC and CynApps CynLib:
a --->|--| temp -----
|+ | ------>|reg|----> c
b --->|--| -----
|
clock -------------
Synopsys SystemC CynApps Cynlib
---------------- --------------
#include "systemc.h" #include "cynlib.h"
struct adder_reg : sc_module { Module adder_reg (
sc_in> a; In<8> a,
sc_in> b; In<8> b,
sc_out> c; Out<9> c,
sc_in clock; In<1> clk )
// internal signal Always (Posedge(clk))
sc_signal> temp; c <<= a + b;
EndAlways
// adder process EndModule
void add() {temp = a + b;}
// register update process
void reg() {c = temp;}
// Constructor
SC_CTOR(adder_reg) {
SC_METHOD(add);
sensitive << a << b;
SC_METHOD(reg);
sensitive_pos << clock;
}};
Both C-based design systems require their own special pre-processors to
make the macros they use actual true GNU gcc compile-able; it just appears
that CynApps pre-processor "Cyn++" is more adapted to having engineers
write C pseudo-code that's very Verilog-like. See http://www.cynlib.com
and http://www.systemc.org for more. (And, oh, yea, if you download the
System C classes, I'm told they have this odd policy where they assume
you're also endorsing it -- so don't be surprised when your company name
suddenly appears backing SystemC!)
"Verilog seems a whole lot easier than SystemC and I do a significant
amount of C++ programming. If you plan on using SystemC you better go
learn C++ in detail including templates, overloading, etc. so you can
actually understand how the thing works. Also, I assume one can only
do a small portion of an ASIC in C/C++, etc. Much of our ASIC IP,
re-use, or legacy certainly will not be in C/C++. Anyway, it is all
pretty useless until there is a good tool which maps C/C++ to Verilog."
- an anon engineer
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