( SNUG 00 Item 3 ) --------------------------------------------- [ 4/05/00 ]
And you can get a good idea of what these guys are and are not interested
in by seeing how they voted with their feet. All of this data I collected
personally by counting each head in each room in each session:
Monday, March 13 Number Of Attendees
9:00 - 12:15 (MA1) Tutorial on DC, BOA, BRT, WLMs, MC 308
9:00 - 12:15 (MA5) Tutorial of FPGA Compiler II 22
9:00 - 12:15 (MA4) Tutorial on Behavioral Compiler 21
9:00 - 12:15 (MA3) Tutorial on EPIC Tools & RailMill 14
1:30 - 3:00 (TB1) coreBuilder, Asynch Dsgn, Testing IP 103
1:30 - 3:00 (MB2) TetraMax, BIST, ATPG, Scan, DC/XP 117
1:30 - 3:00 (TB2) makefiles, Cliosoft, Synopsys ReOpt 116
1:30 - 4:45 (MB4) Tutorial on EPIC, ACE with VCS 17
3:15 - 4:45 (MC1) OO Dsgn, Dsgn Methodology, FlexRoute 219
3:15 - 4:45 (MC2) Verilog Verification, VCS 102 + 12 standees
3:15 - 4:45 (MC3) Large FPGAs, FPGA Express, FPGA WLMs 31
5:00 - 8:00 Synopsys R&D Cocktail Party Est. 600
Tuesday, March 14
9:00 - 10:15 Keynote Address (Aart's Speech) 327 + 26 standees
10:30 - 12:00 (TA1) PrimeTime, DC, Power 210 + 15 standees
10:30 - 12:00 (TA2) Verilog BFMs, VERA 81
10:30 - 12:00 (TA3) Module Compiler, DC 54
10:30 - 12:00 (TA4) TimeMill, Synopsys SLE, PathMill 16
1:15 - 2:15 (MB1) Soft IP, FPM, reoptimize_design, WLMs 206
1:15 - 2:15 (MB3) OO-VHDL, Behavioral Compiler 31
1:15 - 2:15 (TB4) EPIC PathMill 71
2:30 - 4:30 Panel "Ten Years Of SNUG" 202
4:45 - 5:30 Sun Microsystem's Compute Farm Talk 206
6:00 - 8:00 Non-Synopsys EDA Vendor Fair Party over 500
Wednesday, March 15
8:30 - 11:45 (WA1) Tutorial PhysOpt/Chip_Arch/FlexRoute 216
8:30 - 11:45 (WA2) Tutorial on TetraMax, BSD Compiler 47
8:30 - 11:45 (WA3) Tutorial on Advanced Formality 29
8:30 - 11:45 (WA4) Tutorial on EPIC PathMill 11
8:30 - 11:45 (WA5) Tutorial on Scirocco VHDL 9
1:00 - 4:15 (WB1) Tutorial Special Topics in PrimeTime 137
1:00 - 4:15 (WB2) Tutorial Design Reuse Workshop 27
1:00 - 4:15 (WB5) Tutorial on VCS, Vera, Covermeter 25
1:00 - 4:15 (WB6) Tutorial on System C++ 57 + 9 standees
1:00 - 4:15 (WB4) Tutorial on Power Compiler 34
By looking at which sessions where attendees had a choice, you can see
these designers have a strong interest in: PhysOpt, Chip Architect, DC,
PrimeTime, FlexRoute, reoptimize_design, WLMs, BOA, and BRT. Conversely,
they weren't interested in: TimeMill, PathMill, RailMill, ACE, Vera, and
the new Scirocco VHDL simulator. The "standees" data indicated a surprise
interest (i.e. topics were worth standing for) in: VCS, PrimeTime, DC,
Power Compiler, Verilog verification, and especially System C++. (A
whopping 14 percent of the System C++ talk attendees stood to hear it!)
The overall user attendance for SNUG'00 was 474 customers. Comparing this
to last year's SNUG'99 attendance of 528 customers, you could erroneously
say SNUG (and customer interest in Synopsys) dropped 10 percent this year.
Why would this be wrong? Because in October '99, Boston had its first
local SNUG meeting with 263 customers at it -- explaining the San Jose
SNUG'00 drop. (Oddly enough, Boston SNUG was originally planned with an
attendance of 150 customers in mind; so when 263 arrived, it caused some
serious behind-the-scenes scurrying for the conference organizers!) So,
you could then say that SNUG (and customer interest in Synopsys) grew 55
percent this year (474 + 263 = 737; 737/474 = 1.55 = 55%) -- but that
wouldn't be quite right, either. Apples vs. Oranges and all. So, we'll
just have to track local SNUG stats separately now and leave it at that.
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