( ELSE 06 Item 25 ) -------------------------------------------- [ 06/23/06 ]
Subject: Prolific vs. Zenasis
PROLIFIC KICKS ASS -- Competing in the same space, for some reason only one
user spoke up for Zenasis this year. (Earlier in DAC 04 #42 many were
vocal, but not this year.) In stark contrast, Prolific kicked ass here with
many happy & some not so happy "real" users speaking up for them. This told
me that the designers were really actively using the ProLific tools for real
optimization. (In my book, mixed news is good news; whereas if you're only
seeing happy-happy, joy-joy quotes they're almost always bullshit marketing
ploys crafted to deceive you into buying their stuff.) I'm not exactly sure
what's going on at Zenasis this time around. My congrats to Prolific!
ZenCells have some potential for high-end design; this is impression
from their demo; did not actually use it.
- [ An Anon Engineer ]
We do not use ZenTime/Pinnacle/Chip2Nite... But then again, my focus
is on FPGAs not ASICs.
- John Lockwood of Applied Research Laboratory
Prolific does optimization for power, timing and signal integrity.
It creates new cells with drive strengths that are between the cells
provided in your library. It combines cells of different drive
strengths and can also combine cells from various libraries (fast
versus low power, for example) to create the optimal specialized cell
for your situation.
Prolific improves timing by swapping cells after routing. Zenasis sells
tools that create new cells to speed your critical path in a COT flow.
They identify groups of cells in your critical path and create a single
new cell, which may involve reducing the number of logic levels, sizing
transistors, etc. The Zenasis tools interact with Cadabra and Calibre
to create layouts for the new cluster cell. They claim a 10% to 15%
speed increase. Their tools work with Synopsys, Cadence and Magma;
foundries they support include TSMC and UMC.
- John Weiland of Intrinsix Corp.
ProTiming works in conjunction with PrimeTime to generate ECOs for
post-route optimization.
In the past we used our own scripts to generate ECOs based on PrimeTime
analysis. The issue we saw was convergence and precision of the ECOs.
Our script would typically come up with a number of gate sizing changes
to improve timing, but the timing would in many cases not converge
because of legalization issues during the ECO.
Since ProTiming relies on other place and route tools for the ECO, our
expectations for this tool were pretty low.
We ran ProTiming on our design (264 K instances), and it reported a WNS
improvement of 10.2% during optimization. The ECO involved ~3000 cells,
and after ECO legalization and routing most of the improvement on WNS
were intact (9.6%). To achieve ~10% WNS improvement in a single ECO was
much better than we expected. We saw that ProTiming has really good
optimization algorithms targeted for safe post-route optimizations.
Regardless of flow (Synopsys or Magma) we see room for a tool like
ProTiming. It automates final timing and power finishing of blocks.
- Lars-Olof Svensson of Xelerated
Prolific is quite useful if your timing sign off tool comes from a
different vendor as compared to the physical layout tool. This may
be exacerbated once we go away from NLDMs and move towards ECSM vs
CCS timing models.
- [ An Anon Engineer ]
I haven't personally been using ProTiming since a project 2 years ago,
so I'm afraid I don't have good recent data. I'll copy a co-worker.
I believe he tried ProTiming on a more recent project here at AMD and
may have something to add. I know he didn't find it to be as useful
as I did. He was running the same design on a newer process, richer
STD cell library, and newer Synopsys tools: IC Compiler, latest Astro.
It seems one or more of those variables negated ProTiming's benefit
for our particular design.
- David Oliver of AMD
We have not used ProTiming for a year now, so I do not have any new
data. Sorry!
- Sudhir Chandratreya of NeoMagic Corp.
We incorporate Prolific's tools to generate standard cell libraries and
have been an user for about 1 year. The advantages are two fold:
1. the mask engineers are freed up to do the custom blocks.
2. for a company with products that target many different process
technologies, a layout automation tool like ProGenesis is quite
helpful in getting those process libraries out.
ProGenesis can be picked up rather straightforwardly for a casual user
with some pre-defined settings. However, since it does have a lot of
knobs embedded with Tcl/Tk commands that control the layouts, you
need to be an experienced user or have plenty of help from the Prolific
AEs to be proficient at it. Also, it would be difficult for any new
user to debug problem cells without AE support. Luckily, we do receive
good AE support.
The ProGenesis layouts are usually satisfactory and they meet DRC & LVS.
However, some of their layouts still require manual interventions (i.e.
re-generation of layouts with specific settings to improve quality).
Some of the quality issues include wasted track, wide metal spacing
violations, poly/diffusion contact strappings, and undesirable M1
boogers/bumps/protrusions.
There's a BIG difference in ProGenesis runtime for simple and complex
cells. Just to give you some flavor, simple inverter and NAND/NOR
gates may be created in 3 to 5 minutes; but, some of the FFs require
more than 24 hours of machine time to generate.
- David Chiang of Spansion
We have been very happy with the ProGenesis and ProSticks tools. Our
standard cell libraries usually have 30-50 unique cells (4 drive
strengths for each). We require a quick turnaround time for these
libraries due to frequent process changes. We have found that
Prolific's tools do a good job of meeting that demand.
Prolific's customer support is prompt and has usually been able to
answer our questions. They have also been able to support our need
to implement uncommon design methodologies.
One thing that is lacking is a good user manual. ProGenesis has a mess
of Tcl commands but they are hard to track down. Some of its more
useful commands are not documented and only came to light through
working with customer support.
- Joe Tostenrude of Boeing Phantom Works
Our experience with Prolific's ProPower tool has been amaizingly good.
I've never evaluated a tool before that so dramatically optimized a
characteristic of my design while at the same time being trivially easy
to set up and run. Within an hour of first using ProPower, I had taken
my leakage down 50% on a multi-vt design that had already taped out.
This was even after following state-of-the-art vt distribution methods.
Timing got BETTER. No re-route. Formality passes. The tool found ways
to reduce my low vt cell count DRAMATICALLY. I've been in this business
for 20 years now, and I've never seen a tool that had such a large
effect on a characteristic of a design for such little time invested.
If you are concerned with leakage or vt ratios, ProPower is a no-brainer.
- [ An Anon Engineer ]
Prolific ProTiming & ProPower:
Our design is a 130 K placeable instances R/W channel using a 90 nm low
power process. Our target product being a hand-held device, so reducing
power was naturally one of our main challenges.
We used Synopsys Power Compiler inside of Design Compiler and PhysOpt,
together with multi-VT libraries and an activity file to get a power
optimized placed netlist. (Note also that my objective was primarily to
get the best possible dynamic power without giving up too much on
leakage.) In this context, having an activity file is paramount. Only
by knowing precisely the activity on each net can a power optimization
tool figure out if timing slack should be traded for leakage (swapping
from low to high VT) or for dynamic power (down-sizing).
Up to placed gates, I thought that I had a good power optimized netlist.
Actually, the dynamic power of my mixed VT implementation was pretty
much the same as a pure low VT implementation, whereas the leakage was
4 times less (only 2X the leakage of a pure HVT implementation).
Unfortunately for the rest of our flow (placed gate to GDSII) I had to
use Astro, and to my knowledge, Astro does not do activity-based power
optimization. First of all, Astro will revert a bunch of cells to
low VT every time it needs to fix a timing violation, whether it is
after Clock Tree Synthesis or after Routing. Astro has this
astPowerRecovery function which will try to revert low VTs back to high
VTs, however doing so without activity information, may not always be
good for dynamic power.
Bottom line, going through Astro, if I abstract the power in the clock
tree, the dynamic power in the rest of the logic stayed about the same
(+1%), whereas the worst case leakage increased by 78% (without using
astPowerRecovery)!
This is when I decided to look at ProPower from Prolific. This tool
works off a PrimeTime session (typically the one resulting from your
sign off), analyzes your design and its timing slack, and operates
cell swaps to reduce the total power without affecting the timing. The
two main modes of operation are VT swap only and/or downsizing. The
first mode will work only on the leakage, whereas the second one will
also reduce the dynamic power.
So I gave ProPower my sign-off STA database, and since I did not want to
go through an ECO, I limited it to VT swap only (same footprint). The
results were great. Basically, keeping my dynamic power unchanged I
recovered 40% of the leakage (only 7% above the post-placement value).
The runtime was only a couple of hours.
Another experiment I wanted to try was to completely turn off the power
optimization in the whole flow, using only low VT cells and then run
ProPower to recover as much leakage as possible. The reason for this
experiment was that a traditional timing/area aware flow usually
produces the best dynamic power results (since dynamic power reduction
goes naturally with area reduction), but also because turning on power
optimization significantly increases the optimization runtime (DC and
PhysOpt) by a factor up to 4X.
Keeping the same limitation (VT swap only), ProPower was able to reduce
the leakage by 60%. Unfortunately, this result was still 50% higher
than the one coming from a mixed VT power optimized design.
Since I was looking at Prolific I also tried ProTiming. ProTiming takes
the same input as ProPower (actually ProPower lays on top of ProTiming)
and works on fixing the timing violations.
In our case, although we leave Astro with no timing violation, our
(in-house) timing sign-off STA flow based on Star-RCXT and PrimeTime
never completely correlates with Astro STA, and we always end up having
a couple of hundred setup violations, with up to a couple of hundred
picoseconds WNS. The problem of course is that since Astro and sign-off
do not compute the same delays; it's very difficult to predict how many
ECO iterations it will take to converge to a timing clean layout. The
Turn-Around-Time can easily range from a couple of days to a couple of
weeks, which is really annoying when you are getting close to tapeout.
The beauty with ProTiming is that the tool is working off your sign-off
STA session. Therefore, each modification is correctly timed by
construction. If on top of that, you have a mixed VT design, you are
very likely to be able to fix your timing violations doing only VT
swaps and therefore no physical ECO.
This is what I tried on my mixed VT test case and the tool fixed all
the violations in few minutes. Then, all I had to do was to update my
layout and to rerun the STA. (Since the routing did not change I did
not even have to rerun the parasitic extraction.) Technically, I
could have skipped rerunning DRC/LVS, too.
I also tried the same thing on my pure low VT test case (before running
ProPower). Of course, in this case the only way to fix setup violations
is by up-sizing cells and eventually doing an ECO. And that is what the
tool did, once again in few minutes. But I was impressed by the limited
number of changes the tool ended up doing.
Prolific being still a small company, I must say that the support I had
was excellent. In particular everybody was very responsive to my
technical requests (probably more than what is commonly expected from
an EDA vendor during a pre-sale evaluation).
Now, our next step will be to try the full blown power optimization
capability of ProPower, allowing both VT swap and down-sizing, and also
using activity information. I am really looking forward using these
tools for our next tape out.
- [ An Anon Engineer ]
SDS K-Route -- very powerful with surprising results.
- [ An Anon Engineer ]
Man, I haven't even heard of half of these companies. Does anyone have
the budget to risk on this bunch of little guys? Too many choices to
pick a winner yet.
- [ An Anon Engineer ]
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