( ELSE 06 Item 12 ) -------------------------------------------- [ 06/23/06 ]
Subject: ViASIC ViaPath/ViaMask, LSI RapidChip, Altera Hardcopy, Magma SA
SNAPSHOT VIEW -- Some of these user comments were written before Synplicity
and LSI Logic pulled out of the Structured ASIC business -- the rest were
after. You can actually watch the train wreck as it is actually happening
in the customer quotes! What's also interesting is how the Magma SA users
are dedicated to Structured ASICs no matter what. (I'm not sure, but I
think NEC and Altera are still in the Structured ASIC game.)
LSI Logic sells their RapidChip Structured ASIC. They emphasize that
they use fine grain architecture as opposed to NEC so they claim better
performance and density. Their devices can contain memories, SERDS and
PLLs. They use only 4 metal layers to save on NRE. They have no fixed
clock network so it can be customized to your needs. They have hard
macros for processors (like ARM) that have "landing zones" on their
arrays, which will keep them close to cache memory, etc. Some arrays
have a big a big matrix of RAM that can be configured into any size and
shape of RAM and includes BIST logic. The designs are done using
Synplicity Amplify.
Altera sells two main lines of FPGAs: the low cost Cyclone line and the
high performance Stratix line. The Cyclone line was designed for 90 nm
specifically for cost reduction. One interesting set of devices they
have is their "Hardcopy" series. They will take an FPGA design and turn
it into a "Structured ASIC" design, using two metal layers to customize
their base array. They guarantee a successful transition from the FPGA
to the Hardcopy device. Because only two metal layers are customized,
it minimized mask NRE and they can provide parts in only 8 weeks. They
claim logic is reduced up to 85% in size, though memories and I/O stay
the same size, resulting in up to a 90% cost reduction. They see this
as fitting in the middle of the life cycle. Initially customers might
use a FPGA because they are not positive the design is finalized and
because they want to minimize time to market, then when production ramps
up they can go to the lower cost Hardcopy device, then when production
tails off and becomes uncertain they can burn FPGAs as needed for
end-of-life production and for spare parts.
- John Weiland of Intrinsix Corp.
Structured ASIC are too soon to tell. My guess is that boring FPGAs
will win because they have momentum.
- Dave Chapman of Gold Mountain
Structured ASICs are of no interest to us since we use FPGAs because
they're field programmable!
- [ An Anon Engineer ]
Have had nothing to do with Structured ASIC's or even looked into them.
If it's worth your while to get out of FPGAs why not just go to ASIC?
- [ An Anon Engineer ]
I've always been somewhat suspicious of the "huge growth" predicted in
Structured ASIC. I certainly think that there is a place for it in
certain designs where you need a clear path from FPGA when you go into
volume or need to differentiate.
- [ An Anon Engineer ]
Structured ASICs seems to be a failed area since the chips we work on
are, on one hand, very complex and, on the other hand, need to be done
cheaply. Both these seem to be against the nature of Structured ASICs.
- [ An Anon Engineer ]
Structured ASIC is still a viable technology. Just my opinion, but I
don't think LSI was predisposed to really sell Structured ASIC. They
are basically a standard cell company calling on standard cell
customers. Most of their designs really want to be standard cell
designs, yet take advantage of the low NRE and shorter cycle time of
Structured ASIC. In order to get the real benefits of Structured ASIC,
you have to be willing or able to live with the limitations.
- [ An Anon Engineer ]
We were starting to get interested in Structured ASICs, had LSI come
give us their presentation, then got the news that they were not going
to do new Structured ASICs. I wonder what a fabless LSI will have in
5 years, storage? I wonder what Wilf would do.
- [ An Anon Engineer ]
I've been supervising projects using the ViASIC's ViaPath/ViaMask
solution at 0.13 um. ViaPath provided an efficient implementation
and satisfied our requirements. Our tests concentrated on the
Structured ASIC implementations in the range of several thousands
of ASIC-equivalent gates.
- [ An Anon Engineer ]
I'm using ViASIC's ViaPath/ViaMask technology. What I have mainly
found from a recently silicon run is it is a great improvement over
the last year's ViaPath release in terms of timing closure. The
density figures still remain a competitive advantage of this
technology since with only one via-layer available for the routing,
I was able to cope with complexity typically addressed by new
gate-array technologies. Still some work at library level has to
be done to guarantee the interoperability with third party tools.
- [ An Anon Engineer ]
ViASIC sells a via programmed Structured ASIC. They provide the fabric
and the software that maps a Verilog netlist to it. They have Synopsys
models for their cells made with TSMC 0.13, IBM 0.13, Dumgbu 0.13, etc.
The tool outputs SDF for post-route simulation. They utilize separate
logical (synthesis) and physical (delay annotation) library files. They
have a limited variety of physical cells yet a large variety of drive
strengths by paralleling cells. Their tools route the clock through the
fabric that also contains RAM cells, with each bit of RAM occupying
roughly the area of one gate. Instead of having separate areas for RAM,
the RAM and gate cells are intermixed to improve routing because in some
cases logic routing can go over the RAM cells.
- John Weiland of Intrinsix Corp.
Synplicity Structured ASIC synthesis appeared to me to be more a way
for some of the Structured ASIC companies to compete with the tools
offered by the FPGA guys. The tool was subsidized by people like LSI
to make it saleable to people used to the FPGA world.
- [ An Anon Engineer ]
Synplicity said their Synplify ASIC tool, similar to CD Ultra, is
selling quite well and ASIC revenues account for 20-30% of the
company's income (remember, though the cost difference in tool types).
They have DesignWare equivalents. Their physical synthesis tool
supports LSI, Fujitsu and NEC.
- John Weiland of Intrinsix Corp.
Synplicity's decision to move out of the Structured ASIC market
basically means large portions of their R&D expenses were, directly
or indirectly (via licenses to customers), paid by LSI Logic. LSI's
decision to withdraw from the market was not caused by a non-existing
Structured ASIC market (although it is growing much slower than
expected) but rather by using a non-disruptive technology. When a
Structured ASIC technology emerges that is disruptive enough, as we
believe our eASIC is, it will change the market and it is here to stay.
Any great technology is worthless without 3rd party support. We (eASIC)
partner with Magma to tailor their Blast Create SA synthesis tool for
our embedded and chip technologies.
- Richard Herveille of eASIC Corp.
Magma's SA tools are basically regular standard cell tools adapted to
work with the environment of structured ASIC. Regular standard cell
concepts have trouble with structured ASIC restrictions, so you have
to do a little extra to make it work. Magma has done the necessary
adaptation to bring full power standard cell tools to the Structured
ASIC market.
- [ An Anon Engineer ]
Magma's vendor-specific FPGA P&R integration needs improvement.
Performance is sometimes more influenced by P&R than by optimizations
which can be done on the netlist.
- [ An Anon Engineer ]
Magma is a Structured ASIC good tool, at the physical implementation we
can see the unique SA floorplan, we can move cells and legalize them to
the sites, and connect constant signal to the power structure. (This
was after constant work together with the Magma guys for over the past
year. WELL DONE.) The 'relations' mechanism allow us to do recursive
search on model, cell, entity, and get values. There is still work
needed on access to all attributes of a cell, model, entity database,
to get all physical, logical info, and be able to change them through
Magma commands (we like/need to do lots of manipulations).
Further more, all the installed scripts/procedures need to be compatible
to the SA flow, i.e. not all of them have SA flags, which makes them not
work properly (e.g. ECO procedures). More attention should be taken to
supply the standard formats (e.g. complementary pin at Liberty).
I would be happy if the Magma design rule files had the same revisions
as the ones from the fab, (we work with UMC and currently the rules
provided match old revisions from the fab).
In summary, the Magma SA tools are the best tools you can get in the
market for SA, however, there is still a lot that needs to be done
with common efforts to make it ideal.
- [ An Anon Engineer ]
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