( ELSE 06 Item 11 ) -------------------------------------------- [ 06/23/06 ]
Subject: Synplicity Identify and Premier (Amplify)
GOOD AND SO-SO -- Synplicity's debug tool, Identify, seems to have traction
with the user base, but there doesn't seem to be that much enthusiasm for
their "graph-based physical synthesis" tool, "Premier". (Olde timers may
know Premier under its old name: Amplify.)
After using Identify to successfully debug a design in the lab.
Identify Pros:
The capability to instrument the design at the RTL level and have the
tool automatically generate the instrumented code is what I think puts
the Identify tool above the others.
It also does a very good job of estimating the resources required in
the FPGA and has very little impact on design performance until you
start to reach the resource limitations of the device, making the tools
have to work harder to meet timing on critical paths.
The debugging capability Indentify offers is something I had not seen
before for RTL designs -- it is very similar to the software ICE tools
available now, but not quite as powerful.
Identify Cons:
You are limited by the free device resources as to how many signals and
how many samples you can obtain.
The ability to configure and control complex triggering (something a
Logic Analyzer does very well) is very unintuitive and confusing. If
the Identify tool provided a GUI-based trigger configuration in the
debugger it would be a huge benefit.
The default waveform viewer used in the Indentify debugger is extremely
poor, very slow, and very unintuitive. If they licensed a more industry
standard waveform viewer for the tool or even offered it as an upgrade
it would be a huge improvement.
As with any new tool, I ran in to a few code constructs that had made
Identify error out, but are legal RTL. On the flip side, Synplicity
support is excellent and quick to respond and attempt to find a fix or
work around for me.
- Shawn Swilley of Microvision, Inc.
Identify is helpful for debugging.
- Rahul Khinvasara of Nevis Networks
Identify is a life saver when you need to debug something in emulation.
It's fairly easy to use and gets the visibility where you need it. It's
saved us weeks of debug time.
- [ An Anon Engineer ]
Identify appears to be a neat on-chip debugging tool, but haven't tried
it personally. It competes with Xilinx's ChipScope. The disadvantage
is Identify is added into the design pre-synthesis, whereas ChipScope
can be added post-synthesis which translates to faster debugging. The
advantage with Identify is that because it is added pre-synthesis it is
easier to identify the signals you want to trace. Oddly enough it's
because of Synplify's optimizations and net renaming that makes it
harder to determine which signals to trace in ChipScope post-synthesis.
You can add ChipScope pre-synthesis, but you have to add it to your
source code yourself. Identify inserts itself into the source code.
Identify is more of a source level debugger tool which allows you to
step through the source code and view signals one clock cycle at a time.
ChipScope is more of a logic analyzer type of tool with no source code
reference but with a much better trace display as you'd want from a
logic analyzer type of tool. It just depends on the type of problem
you're trying to debug and the way you like to debug.
- Richard Hein of Agilent Technologies Canada
We use ChipScope, which is much cheaper and almost as good as Identify.
We are "hands on" with AmplifyRapidChip, but alas, it is about to be
discontinued. Not that it really matters, but AmplifyRapidChip is a
decent physical synthesis tool for the price. It is a very immature
tool compared to its big cousins from Synopsys and Cadence, however.
- Douglas Hundley of Tarari, Inc.
We do use Identify. We have also used Chipscope, but are only using
Xilinx parts so have no experience w/ Signaltap. Chipscope is much
lower level. Since getting Identify I believe our designers use that
exclusively. If you count votes with our $s, we are planning to add
more copies of Identify in the very near future.
- [ An Anon Engineer ]
Synplicity has been our synthesis front-end tool of choice for 4 years.
We use Identify to debug circuits that process so much data that
simulation would take weeks.
- John Lockwood of Applied Research Laboratory
Synplicity has a new Amplify tool for physical synthesis of FPGAs in
beta. It has new placement algorithms that they claim result in better
placement than Xilinx tools. Altera support is under development.
Their Identify tool allows you to debug an actual FPGA in an environment
similar to a simulator; you identify signals to probe, etc. in the RTL
and it handles the details. Identify now handles VHDL or Verilog.
- John Weiland of Intrinsix Corp.
Synplicity Premier (Amplify)? Haven't tried it personally but have been
given plenty encouragement from Synplicity to try it. We try to avoid
FPGA placement if possible. If you need to do placement on a FPGA
you're living on the edge. Has its place for getting that extra bit of
functionality into an already packed FPGA or getting the clock speed up.
Xilinx also has a series of tools to achieve the same end, FloorPlanner,
PACE (both essentially 'free' with the place and route software bundle)
and now PlanAhead. FPGA placement tools seem to vary in the design
information they present to help in deciding where to place, but they
all require manual placement. I don't know why no one has come out with
a semiautomatic area placement tool that can work out optimal area
constraints based on a design's hierarchy, timing and I/O placement.
If any EDA tool vendors are reading this there's $$$ to be made here.
- Richard Hein of Agilent Technologies Canada
Only use Synplify/Amplify. Amplify is not good as expected. Synplify
Pro is better than Mentor's and Synopsys'.
- [ An Anon Engineer ]
We do use Amplify RC for our LSI Rapidchip designs. It seems to be
getting much better but still has some areas that need improvement.
- Michael White of Arrow Electronics
Mentor's Exemplar - very stable, and this what we need.
Synplicity Amplify FPGA - we got same results with similar compilers
that we got from FPGA manufacturer.
- [ An Anon Engineer ]
We use Synplicity's Synplify Pro, and recently evaluated their Synplify
Premier. We were doing final verification of our FPGA, so we gave our
two designs to Synplicity to run in taxicab mode: a Xilinx Virtex 4
LX60 and a LX100. The system clock was 200 MHz, with a max frequency
of other clocks on the designs being 400 Mhz. We also implemented
DDR SDRAM, DDR2 SDRAM and DDR2 SRAM interfaces on these designs.
We had already earlier met our timing constraints on the designs using
Synplify Pro -- the designs were in the final stages of qualification.
Both were ~65% full. Our goal was to evaluate the benefit of using
Synplify Premier.
The Synplicity people did a good job understanding our designs. When
they came back with the taxicab results, Synplicity said the elapsed
time for Premier was only 2-3 hours. Most impressive was that
Premier's timing analyzer correlated within 5% of Xilinx ISE timing
analysis. But the Synplify Pro the correlation was only 20-50%, so
we added more constraints, and configured the Xilinx P&R tool to be
more efficient.
Premier doesn't support the Xilinx Virtex II designs that we have, but
in my opinion it has real potential over Synplify Pro for physical
synthesis. It appears to be better able to perform timing. Also its
graph technology is probably a plus because it takes into account the
real structure of the FPGA and the physical connections on the die.
- Olivier Clozeau of Credence
We use Synplicity Premier, Certify, Identify. There were some teething
problems with Certify and Identify, but those are done. We've always
been happy with Synplicity. The only thing we don't like is they want
beaucoup $$ to float a dongle license that we purchased years ago.
- [ An Anon Engineer ]
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