( ELSE 06 Item 10 ) -------------------------------------------- [ 06/23/06 ]
Subject: Synplicity Synplify Pro and Synplify DSP
YAWN AND I'M AWAKE -- Over the years it's been trivial to find users who
gush about Synplify Pro. (See DAC 04 #6 and DAC 03 #21) <Yawn> No news
there. But these comments about their new Synplify DSP got my attention.
I heard it's very similar to Xilinx's Accelchip and Altera's DSPBuilder.
Synplify Pro is used and highly regarded.
- [ An Anon Engineer ]
Synplify Pro continues to meet my needs very well. Although it has
gotten a little slower in recent releases, it was so fast to begin
with, time spent in synthesis is still down in the noise compared to
time spent in simulation and P&R.
Oh, and Synplicity has gotten much better in avoiding making the same
mistakes from one release to the next (as I complained about in
http://www.deepchip.com/items/0427-01.html).
I've been hearing for years that someday I'm going to need Synplicity
Amplify to do physical synthesis in my FPGA design flow. And I still
acknowledge that day will come. But for now, I still get by with
using only Synplify Pro, plus
(a) realistic timing constraints,
(b) pipelining,
(c) retiming, and
(d) specifying multi-cycle timing paths
where applicable. That seems to keep P&R to acceptable durations with
a few iterations.
- Bill Lenihan of Raytheon
We use Synplify Pro, and for the small FPGA's we do, it works well;
easy to use I/F.
- [ An Anon Engineer ]
Synplify Pro is our choice for FPGA synthesis.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
We wanted to implement our Matlab algorithms in VHDL, so we did an
eval of Synplify DSP. Synplify DSP automatically generates VHDL code
from a Simulink model, using blocks from Synplify's DSP blockset for
the part of the model that is translated to VHDL code. To evaluate
Synplify DSP, I ran a relatively small and simple design through the
entire flow. The design's specs were:
- input sample frequency = 15 MHz
- input samples are 12-bit signed values
- input fed to a 3-tap pre-filter with coefficients: 1, 0, -1 to
eliminate DC and fs/2
- output of pre-filter fed to a 9-point I- and a 9-point Q-filter
that produced 20-bits data for both I- and Q-results
- the 20-bit data was decimated by a factor 8 and rounded to
12-bits signed output data
After I ran the small testcase successfully, I ran a more complex
design (beam-steering calculation) which we had already completed, so
we could do a one-on-one comparison of the Synplify DSP results with
our original results.
The beam steering algorithm is used to calculate the switching behavior
of 420 dipole-antenna's which control the beam direction of a reflect
array antenna, based on a number of input parameters such as position
of the dipole-antenna, desired beam direction, health state of the
dipole-antenna and some conversion factors. The beam steering
calculation has following specs:
- a set of input parameters, all 24-bit wide signed integers,
with 6 bits before and 18 bits after the decimal point (6.18 format).
- 3 lookup tables with X, Y and Z position values for each dipole
- for each dipole, an algorithm performing multiplications, additions
and subtractions with the parameters and table values is performed
to calculate the phase value.
- the calculated phase value in combination with a 2-bit parameter is
used to look up the corresponding state value in a table.
- from the state value, 2 bits are selected that define the switching
of a dipole-antenna. The selection is made by looking up the health
state of a dipole-antenna in a table.
- the calc is performed sequentially for all 420 dipole-antenna's,
after the detection of a trigger pulse.
I did not run any specific benchmark tests on Synplify DSP's capacity
and speed. This is because the realistic testcases showed it was able
to generate VHDL within a few seconds, which was so fast it can be
ignored compared to other design steps, such as a P&R run.
The Synplify DSP positives:
- Quality of results. Synplify DSP produced VHDL that was readable;
then, after synthesis with Synplify Pro we got the hardware that we
expected, with no unexpected waste of resources.
- Design portability to different FPGA hardware. Synplify DSP supports
both Altera and Xilinx. I have run my testcases for both and it
showed that the results are OK. This is very useful!
- DSP synthesis/architecture optimizations, including automatic
production of multi-channel implementations help make optimal use
of the chosen FPGA technology. For my small testcase the tool
produced a result that I could trace back to my original design. For
the large testcase the design was optimized so dramatically that it
was very hard to link the result after synthesis to the original
design. Simulations showed that the behaviour was still OK, but as
an engineer I want complete control over the implementation and with
these features I have to blindly trust it, which is difficult...
- Its Fixed-point and Full Precision Data Types and Automatic Data
Propagation let you build a very flexible design. When a different
accuracy is needed, I can easily adjust the bit-width and see what
influence such a change has.
- RTL Generation from Simulink. The generated RTL-code is readable and
when it is synthesized, it maps to the logic you would expect.
The Synplify DSP not-so-positives:
- Extension / improvement of the DSP blockset needed. Synplify DSP is
able to generate VHDL only when all blocks in the design are from this
blockset. Synplicity could improve its blockset by adding more blocks
and making the existing blocks more adjustable. Synplicity is very
cooperative here and has improved the blockset with every new release.
I would like to see them go beyond DSP / algorithm design and also do
interface, control logic (state-machines) and glue logic design.
- You have to completely adapt your design flow to this tool, which can
be pretty radical and expensive. For the front-end you have to use
Matlab/Simulink and for the back-end you have to use Synplify. These
tools are very expensive and Synplify DSP is only suited for one
special task (DSP or algorithm design), but when you need this
functionality and you can afford the tools, Synplify DSP is great.
- Testbench Generation. The testbench generation in itself is OK, but
its usefulness is doubtful. Normally, the Simulink part of the design
is simulated against the functional model in Simulink. When this
simulation is OK, an RTL model is generated and this RTL model is
integrated with the rest of the design. The complete design is then
simulated with a dedicated testbench. So when using this flow, the
generated testbench for the RTL model is of no use.
Generating functionality with Synplify DSP is far more flexible than
instantiating IP-blocks. IP-blocks are mostly vendor specific, so we
can't reuse a functional block in another FPGA technology. Also, with
Synplify DSP it is very easy to make changes to a design, such as
changing the bit-width.
Having a common design environment (Simulink) for both functional
(algorithm) design and design implementation was a big advantage for us.
In the past, our algorithm designers made a Matlab model, translated
it to a text-document, and subsequently the HW designer interpreted the
text-document and created a hardware model. This caused a number of
misunderstandings between algorithm- and hardware-designers when they
could not verify the HW model against the functional model.
The results with Synplify DSP required similar resources to our handmade
design, yet we were able to do the large testcase with Synplify DSP in
50% of the time that was needed to do it by hand. I should qualify this
statement... since we used a handmade design as a reference point, we
did save some time that would normally be needed to figure out how to
solve certain problems had it been a new design. Also, since Synplify
DSP is not suited for interface-, control- and glue logic-design, which
are usually also substantial parts of a design, the decrease in total
design time for the complete design will be less than 50%.
- Iwan Hulsman of Thales Naval Netherlands
I use Synplify DSP v2.8 and Altera DSPBuilder v5.1 with Synplify Pro
v8.5 as my synthesis tool. Mathlab/Simulink v2006 plays a big role in
all of this, too. I've used DSPBuilder for 1 year and Synplify DSP
for 10 months.
Altera DSPBuilder Pros:
- Easy to operate, no real need to look at the manual for most designs.
- I love that you can import verilog (or VHDL) as a block. This is
very important because we have the HDL code generator for filters
from Mathlab (we use a lot of filters).
- Enable on most blocks.
- Simulation files work great (we use ModelSim PE +).
Cons:
- The filter generator in DSP Builder is not good!
- It doesn't make frequency you want all the time.
- Biggest word length is only 50 bits (not great).
- You can only output VHDL (we like to use Verilog).
- Customer support is the worst.
Synplify DSP Pros:
- Long Word length supported.
- Customer support is great.
- Achieved much higher frequency.
- With v2.8 uses much less resources of FPGA then DSPBuilder.
Cons:
- Had to call customer support a couple of times. (I could not
figure out some of the blocks.) Manual not the best.
- No Enable on blocks.
- Couldn't use Synplify DSP until v2.8 came out, filter generator
was not good; it produced resource hogging filter with no option
for FIR decimator filters and interpolator filters.
- Still no import of HDL code!!
- Simulation files not so great for Verilog simulation.
About my company: We design and sell test equipment to power companies,
filtered voltmeters, watt meters, impedance meters and frequency
generators. We have been using DSP's from TI to do all the processing
(filtering and math). I thought it would be a good idea to try FPGAs
for this application.
- Alan Jayson of Signalcrafters Tech, Inc.
The strength of Synplify DSP:
1. easy to start
2. reach libraries
3. fast running simulation
4. good support
5. reasonable accuracy comparing to matlab
Problem:
1. difficult to trace the signals in VHDL code
2. no adaptive FIR support
3. no parameter path support from Matlab to Synplify.
- Shlomo Moler of Rafael Israel
I use Synplify DSP for HD and SD video algorithms. When the clock
frequency is up to 80 MHz, it works straight forward. The reliability
is good, what you simulate in Simulink is also happen on the hardware
with the generated VHDL-code. An automatic generated testbench for a
verification check in ModelSim (or other simulator) ensures the correct
generation. You will make more simulations on the PC in the Simulink
environment, evaluation on the hardware is much shorter in time.
Minus:
- At this moment Synplify DSP generates one 'flat' VHDL file, no
hierarchy. (possible in the future)
- Also needed Synplify Pro for retiming, an expensive tool.
Plus:
- Generates general VHDL file, not vendor specific.
- Easy to make cumstomer libraries, compare with Altera DSPBuilder.
- Reliable functional generation, no debugging in VHDL or on the
hardware.
- Easy to simulate in Simulink instead of test benches in VHDL and
ModelSim.
We have to invest more effort for algortihms on 150 MHz or even 225 MHz.
The functional behaviour is correct. The amount of resources (logic
elements) are much more than we expected. We will look closer to what
is happening, so no conclustion yet.
- Co Nelen of Thomson
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