( ELSE 06 Item 8 ) --------------------------------------------- [ 06/23/06 ]
Subject: Synfora Pico, Celoxica Handel-C, Carbon DesignPlayer, Summit
ALL THE OTHERS -- While Mentor Catapult C and Forte Cynthesizer dominated
the mindshare in the C discussion, there was a small posse of other C-based
tools who deserved honorable mention. Synfora makes a customer processor
and compiler (a la Target Compiler Chess/Checkers or TenSilica) from you
application's C code. Celoxica does something similar but for FPGAs.
It takes a bit of a mind set change to think of HW generation with C.
There is a pretty long learning curve for someone involved in RTL design
to code their algorithm in the right flavor of C and also in the right C
structure, push the tool buttons to get to optimal HW.
Synfora has an excellent SW driver generator and auto testbenching
methodology. Lack of C++ support makes C code targeted to HW cumbersome
to write. Runs a little slowly for large designs. ASIC centric.
Celoxica Handel-C is well integrated, supports clock domain crossing,
etc. Takes a while to learn to get to full productivity, though. Seems
like Celoxica is going to be switching to SystemC in the future. FPGA
centric. My previous project had 1 SW guy write the code for an entire
FPGA with a little bit of help from a HW guy, in about half the time it
would have taken 2 HW guys to do the same, minimal bugs as well when we
got in the lab. Great productivity booster!
Catapult is our current choice due to the control it offers on HW and
interface synthesis. Works fast, easy to use, C++ support, would say
this tool is the most HW engineer friendly though the buttons you can
push end up being a bit overwhelming! Equally good support for FPGA
and ASIC designs.
Looked at Y Explorations, their tool works but is very difficult to
understand and use. Technical support is mainly targeted at Japan so
local U.S. support is rather meager...
- [ An Anon Engineer ]
Synfora sells a customizable VLIW processor but they say they can do the
rest of the system as well using their C language behavioral synthesis.
Their tool creates a number of versions of their processor and allows the
user to make speed/area/power tradeoffs. They have pre-characterized
TSMC 0.13 library and say they can quickly bring up other libraries
using scripts. Unlike some competitors, it is now possible for the user
to assemble custom instructions. Synfora accomplishes this using a C
and Verilog description from the user. The tool is sold on ease of use
rather than configurability.
YXI sells a tool that goes from ANSI C to VHDL or Verilog RTL. They
also have worked with Renesas and now can use the HyC language, which
has more timing information than untimed C.
- John Weiland of Intrinsix Corp.
Mentor Catapult C: is the most used C-to-RTL tool, so more bugs found by
design community. Good tool as a first step for C-to-RTL. Good results
on basic stand-alone blocks. Known limitations still exist and 2006
version is below my expectations in terms of progress.
Forte Cynthesizer: C-to-RTL. Interesting results on large models. Still
some problems to solve that can make the results unstable. They're the
one that really supports SystemC level timings when we need it.
Synfora: C-to-RTL. Great results achieved on trials done. Seems to
create difference with competition when many blocks to synthesize.
Bluespec: BSV-to-RTL. Problem solved is not the same than other tools.
Waiting for the C version.
- [ An Anon Engineer ]
We found Synfora Pico ideal for algorithmically oriented processing
applications such as JPEG encoders, video codecs, AES, Static Huffman,
etc. These applications implement C level algorithms into hardware.
Synfora allowed us rapidly analyze and build various RTL implementations
that trade off gate count, clock frequency and resource utilization.
The resulting RTL is balanced and can be implemented at first pass in
silicon without design iterations. Our experience for DSP-based
applications, Synfora is the best match.
- Rahul Shah of eInfochips
Celoxica Handel-C tools have potential. I've adopted them in my course
programs and plan to augment VHDL in the classroom with Handel-C.
- John Lockwood of Applied Research Laboratory
In comparing Catapult C vs. Celoxica Handel-C, we found that behind
Catapult C is the better idea. Using pure C/C++ gave us the most
compatibility to the rest of our company flow. We were able to trade
off between different micro-architectures for the same functionality.
We were able to get production quality results for high sampling rate
designs and to control poor low sampling rate designs in a short amount
of time -- no chance to do that jobs by handcoding RTL. By the time it
gets to more control or lower sample rates the tool still has problems
to find small solutions. In this case results could easily get 2 to 4
times larger compared to handcoded RTL.
- [ An Anon Engineer ]
VaST Systems sells models for common processors, allowing users to do
virtual prototyping to debug software. These models are cycle accurate
at an architectural level and help with bus structure, cache sizes, etc.
They are intended for hardware/software codesign: software engineers can
write their code while hardware engineers create more detailed models.
Tenison EDA sells tools for converting Verilog models into C and C++
models for verification and software/firmware development. They have
various tools for linking models with firmware, testing C models versus
RTL, and exporting stand-alone models. VHDL tools are in development.
Bellum Software sells a graphical tool that allows the user to design
and simulate at the transaction level. The say this allows rapid
debugging of protocols and exploration of new architectures.
CoFluent Design is a French company that sells a high level graphical
tool. The input is a graphical model plus some C code for functionality.
The output is a C++ executable model, similar to a Matlab level model,
used for timed behavioral modeling. They say their system can mix
control and data flow on the same diagram. Their goal is helping system
architects quickly do tradeoffs.
Bluespec sells a tool that takes extensions to System Verilog that
basically describes constraints on your design, and outputs Verilog RTL
and cycle accurate C models. They claim to average roughly a 50% time
savings (in one case as much as 80%) in getting to a verified netlist,
but say customer evaluations have shown only 2-3 days of training is
necessary to become productive.
NEC has been using C based tools for 10 years and is now offering them
to customers. They have translators from C to VHDL or Verilog and vice
versa and also an equivalence checker than can compare the two. It can
also generate bus interfaces like AMBA and AHB and includes a formal
property checker as well as a floorplanner. These tools can produce a
cycle accurate C model for ISS. NEC asserts that most of their bugs are
now found in C simulation, not RTL.
Poseidon Design Systems sells two tools. The first is a C based system
that analyzes the software on the system architecture, performing
transaction level co-simulation to identify bottlenecks. The second
creates an FPGA accelerator for slow instructions and creates the
interface for the processor to the FPGA.
Carbon Design sells C based verification systems (the symbol for Carbon
is "C" - get it?). They emphasized that C-based simulation systems are
much faster than RTL. They also highlighted the cost advantages that
once you get the system running you get as many copies as you need for
free, unlike hardware based systems. Their system accepts RTL in and
can connect to models from CoWare, VaST and ARM.
- John Weiland of Intrinsix Corp.
All things considered, I'll put in a plug for Carbon's DesignPlayer;
easy to use and a high quality robust tool. Its got a small niche,
but sure, very useful and usable therein.
- [ An Anon Engineer ]
Been using Summit Design System Architect for architectural exploration
for several years. Very happy with System Architect, which allows you
to record to a database and analyze the results later. Summit has no
real competitors for this tool.
Not so happy with the Visual Elite part. It has the same problems as
all graphical entry tools do. As long as you stay within the narrow
guidelines of using Visual Elite in the defined way everything is fine,
but if you need to venture outside of these limits the tool can be more
difficult. This has improved substantially over time, but it still has
difficulties with certain things. This has a lot to do with C++ giving
you enough rope to hang yourself.
Picked up Vista last fall and after initial teething problems its now
solid. We are expanding our use of Summit tools.
MaxSim is very good at the ARM/bus interface and for profiling firmware.
However, it needs substantial improvement in debugging and integrating
SystemC modules. The only real way to debug a SystemC module in MaxSim
is using printf's, because MaxSim simply crashes when there's a problem
in a SystemC module.
- [ An Anon Engineer ]
We use Cadence Incisive and SystemC. The SystemC and SCV integration is
done well. Have not compared the performance of Cadence SystemC kernel
to that of the OSCI version. I have been disappointed on how difficult
it is to move from one release of the Cadence tools to a new release.
Even incremental releases (i.e. 5.6v2 to 5.6v3) are always a struggle.
Most of the issues are related to features in the SystemC library and/or
kernel. Cadence needs to improve quality in this area.
- [ An Anon Engineer ]
C-based EDA tools suck. Did the people who wrote these things ever
design a chip??? Also, you left out "TestBuilder." It sucks, too.
- Dave Chapman of Gold Mountain
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