( ELSE 06 Item 7 ) --------------------------------------------- [ 06/23/06 ]
Subject: Mentor Catapult C
WORLDWIDE -- In purely technical terms, Catapult's biggest rival is Forte
Cynthesizer. While Catapult C claims it can read straight olde sequential
ANSI C, Forte uses "timed" SystemC as source code. In terms of geography,
with their much larger marketing budget, Mentor Catapult C users are many
in Japan, and with some in Europe and India -- whereas the Forte universe
seems centered mostly in Japan. Neither companies seem to generate that
much interest in the U.S. chip design market, though. Synfora Pico and
Celoxica Handel-C seem to be the smaller players in this space.
We did an eval between Mentor Catapult C and Forte Cynthesizer for a
NTSC encoder design. Catapult C generated RTL was slightly smaller
than Forte's results. For 27 Mhz, both produced designs of roughly
the same performance. Results after Synopsys DC synthesis:
Mentor Catapult C RTL: 247 K um2 (98.4k gates)
Forte Cynthesizer RTL: 249 K um2 (99.2k gates)
Post-DC analysis: Forte's area estimates before running DC are better
than Catapult's estimates. Forte result is very close to the post-DC
results, because Forte generates many dont_touch attribute script for
DC. However, Forte does not have wire load nor scan synthesis
settings, that is expected to make the worse timing result after DC
fanout adjustment. Catapult area estimate is not the same post-DC
result. Catapult does not estimate all area before Design Compiler
synthesis (roughly 20-30% smaller).
The biggest difference we noticed was implementation time. Catapult
was 10 times faster to RTL than with Cynthesizer. Catapult was able
to accept our original ANSI C++ algorithm with minimum changes; which
was the biggest reason for the difference. Cynthesizer required
extensive modifications of our original ANSI C++ algorithm with
SystemC constructs and directives, increasing our coding time.
We also found Catapult's graphical user interface very useful for
analyzing the design and achieving good results.
- Yoshinao Umeda of Prime Gate, Ltd.
We looked at Mentor Catapult C and Forte Cynthesizer. Forte was not
considered because it needs timed SystemC models. Catapult takes
untimed C/C++ models, which fits better to our flow. We have evaluated
Catapult and bought some licenses. We are now starting to use it in
project context.
- [ An Anon Engineer ]
Forte Design Systems sells a behavioral synthesis tool that goes from
SystemC to Verilog RTL. They emphasized that it is production proven.
Mentor's "Catapult" goes from C++ (with no timing in the code) to RTL.
They emphasize that they take standard ANSI C++ as input but support
SystemC data types. It builds RAM interfaces automatically. You also
need to specify clock rate and other constraints as an input. Outputs
are cycle accurate VHDL, Verilog and System C (for simulation) and VHDL
and Verilog RTL. Unlike Celoxica's tool, theirs inserts registers
automatically based on constraints. Their tool is probably not as good
at what-if analysis or HW/SW tradeoffs. They say it's aimed mainly at
dataflow applications with minimal control issues.
- John Weiland of Intrinsix Corp.
We were SystemC Compiler users and recently switched to Catapult C after
an extensive evaluation. Catapult is mature both in features and ease
of use. We could use our original C spec as input into Catapult, so
many engineers can easily learn the tool. The performance is good but
depends on the end application.
- [ An Anon Engineer ]
I was in charge of evaluating Catapult for awhile last year. We design
image processors, and certain datapath-centric algorithms we implement
map very nicely to the Catapult C flow. We started by taking an
existing DSP block we had modeled C code as well as VHDL RTL, and using
Catapult-C to generate RTL as a comparison.
Mentor's AE's were great in helping us get up and running, which mainly
required modifying the C code to conform to Catapult C coding guidelines
as well as changing some data types to map to Catapult-friendly revs.
Once the input and output interfaces on the block were defined, Catapult
was then able to generate RTL code with a flexible number of pipeline
delay stages, allowing us to make trade-offs between total throughput
and number of gates.
It was pretty slick, although required quite a bit of modification to
our original C code. At that point I was put on another project and
didn't get to fully complete the evaluation, but I believe our company
ended up purchasing the tool and is now working on putting it into
production.
- [ An Anon Engineer ]
Feedback on Catapult C:
+ The tool substantially reduces design time for datapath design. This
is because, it synthesizes the algorithmic C++ code to RTL depending
on the library characterization and architectural constraints.
+ Automated verification flow substantially reduces the time required
for the blobk-level verification.
- RTL generated is unreadable and highly structural.
- RTL generated may not be optimal in performance (for ex: area).
- Sheetal Kumar Jain of STmicroelectronics
Catapult C is a good tool on a right track, but still need some time to
became great. I personally think that a behavioral synthesis tool,
first of all, should be a good parallelizing compiler. It can be used
as a fully automatic tool with good results for most C programs. Or a
lot of advanced compilation optimizations can be done by the tool, such
as pipelining, and data prefetching.
Don't like Handel-C nor Bluespec.
- [ An Anon Engineer ]
My group has been using Mentor's Catapult C for the past 3 years on
several projects with good results. The original impetus for using the
tool was the need to quickly prototype complex wireless receiver
algorithms which could require several man-months to hand-code in VHDL.
We found that Catapult-C reduced this design time to a few weeks which
enabled us to comfortably meet our tight schedules. The tool has
matured since then and is now used globally in Nokia.
My group is currently using Catapult C to efficiently analyze hardware
architectures and complexities for various next-generation wireless
algorithms. Although Catapult C is not applicable to all of our designs
(there really is no tool that can do it all) it is definitely an
integral part of our design flow allowing us to give our customers a
good assessment of the hardware complexity for various physical-layer
algorithms. We feel that Catapult-C is the most mature behavioral
synthesis tool on the market today.
- Dennis McCain of Nokia
We evaluated Catapult C for our behavioral synthesis methodology. We
graded the tool on three important points:
- amount of modification required in original C spec
- RTL functional verification environment
- RTL quality of results.
We used 4 evaluation designs (including JPEG encoder, YUV transform).
Catapult can generate several architectures from one C source. ASIC
library characterize takes a long time, but we were able to create
C IP that's not dependant on process technology. This is a good point
also. To summary, we are happy with results of evaluation and we will
adopt Catapult for our high-level synthesis flow.
- Masahiro Oie of Casio Computer Co., Ltd.
I have worked with Catapult and I like it. I think the value it brings
is two fold. First it shortens the design investigation time by quit a
bit, and second, if you are developing new algorithms it does not tie
you to predefines primitives like Synplify DSP and the others do. The
verification chain is pretty smooth as well since the Catapult tools
are well integrated.
- Irfan Nasir of Motorola Labs
We chose Catapult primarily because of the maturity of the tool and the
fact that it supports both ASIC and FPGA targets -- a prerequisite for
doing real-time FPGA prototyping for system validation and before
switching to an ASIC technology for the final silicon.
While good hand-coded RTL code may yield slightly smaller silicon, the
overall cost and time-to-market constraints are in favor of C synthesis,
even for our high volume products.
- [ An Anon Engineer ]
First we tried another behavioral synthesis C tool for 3 weeks, but
couldn't create a working design for an FPGA. We spent much time
changing the original C-code and running simulations. Next we tried
Catapult C. It was easy to use and we got a working design for an
FPGA in a few days. We changed the original C-code a bit in order
to meet our performance requirement. We were satisfied with the
results.
- Tsuyoshi Sakamoto of Pioneer
Index
Next->Item
|
|
