( ELSE 06 Item 6 ) --------------------------------------------- [ 06/23/06 ]
Subject: Forte Cynthesizer
MOSTLY JAPANESE -- In purely technical terms, Forte's biggest rival is Mentor
Catapult C. Forte uses "timed" SystemC as its source code, while Catapult C
claims it can read straight olde sequential ANSI C. In terms of geography,
most of the Forte universe seems centered in Japan; whereas, with its much
larger marketing budget, Mentor Catapult C users are many in Japan, and with
some in Europe and India. Neither companies seem to to have generated much
interest in the U.S. chip design market, though. Synfora Pico and Celoxica
Handel-C seem to be the smaller players in this space.
I am a Japanese engineer. We have been using Forte's Cynthesizer since
2003 when we first purchased it. We are very happy to see their new TLM
support and will consider it in future designs. I'm interested in the
routability of layout from RTL generated by Cynthesizer. We have not
met the routability problem yet, but I think it will be occurred.
- [ An Anon Engineer ]
SystemC is the standard since December 2005; I would downgrade any EDA
vendor not supporting it. From recent Toshiba reports Forte Cynthesizer
seems a good tool; I don't have personal experience with it.
Looks like MathWorks Matlab & Simulink are still the leader.
- [ An Anon Engineer ]
Oki switched to C-based design using SystemC to reduce the implementation
time for algorithms in hardware with acceptable QoR. SystemC gave us
fast system verification at the front end of the design process including
co-design of software and hardware. However, it moved our bottleneck to
the C-to-RTL implementation stage, so we needed more automation there.
We began using Cynthesizer in the fall of 2004, and have since used it
to complete several projects. For our first project, it only took about
3 months to implement two functional modules for our production LSI
design. Even our SystemC "beginners" had their development time cut in
half. Follow-on projects with Cynthesizer took approximately 1/3 less
time that it took us to create the RTL by hand.
For area, our benchmarks of Cynthesizer's area results range from 80%
to 130% of conventional hand-coded RTL design. On average, Cynthesizer
produces roughly the same area as hand-coded RTL.
What we liked about Forte:
1) You have far less hand RTL implementation work with Cynthesizer.
We can use our old C/C++ description (except for the I/O interface
part of the design where we use SystemC to describe timing.) For
optimization, Cynthesizer allows timing-based scheduling, where we
can control fine scheduling with synthesis options and directives.
You can use auto-scheduling to ensure functional equivalence between
pre- and post-synthesis and automatically verify the results with
the same testbench.
2) You can more thoroughly explore the design space with various
latency constraints, which is highly useful to us. Cynthesizer's
synthesis is extremely high speed -- we can synthesize approximately
30 K gates in several minutes.
3) Your specification can be changed quickly prior to layout. For
example, we found a defective process equalizer in our design during
LSI verification. Using Cynthesizer, we were able to modify the
code and re-verify in only 4 hours. With conventional RTL design,
this would have taken us 4-5 days.
Drawbacks:
1) We need equivalency checking between SystemC behavior and RTL. We
have to do this with dynamic simulation. Honestly speaking, it is
a time consuming step and something that needs fixing in the future.
Behavioral synthesis is an emerging technology and everything is
not mature yet as it is with RTL. Perhaps you would agree that this
was also true for the early days of Synopsys Design Compiler... so
we are taking some risks to move us forward.
2) ECOs are difficult to do during layout. We had that equalizer spec
change occur during place and route. We gave up doing an ECO on our
design for this change because we couldn't find the relationship
between the SystemC code and the netlist. So we restarted from the
logic synthesis step, which caused a 1 week delay to discover this.
In contrast, a conventional RTL design could have dealt with the
same ECO within a day.
So far we have completed 5 modules using Cynthesizer, and 4 LSI's. With
it, we consistently achieve a 1/3 decrease in the overall design time
compared to hand-coded RTL. For example, for a recent LSI design we had
a 17 month LSI development time, which we were able to reduce to only
12 months using Cynthesizer! Oki has a wide variety of algorithms to
implement in a very short time period, so this is an important advantage.
- Kazuhiko Maki of Oki Electric
We got a demo of the Forte Cynthesizer product. As a "third generation"
product, it got the best reviews for completeness and usefulness of the
results from the EDA industry analysts.
From our point of view, Forte's sample problem (the scaler module of an
MPEG decoder) must have been selected by their sales *prevention* dept.
After the first run yielded a 140 K square micron die size, against a
constraint of under 125 K, they showed how the engineer could (manually!)
inspect the resource utilization to determine that two internal blocks
consumed 120 K square-microns, while the remaining ~18 blocks used the
other 20 K. They then popped up a window into the generated Verilog
from which it became immediately apparent that the area budget was blown
by the instantiation of 18 fixed-point multipliers. Another few clicks
hot-linked to the appropriate C source code, which had 3 sets of 6-term,
linear sum-of-products, in which all of the coefficients were constants.
(Note: I last wrote a compiler 22 years ago, and at that time, it was
already common practice to optimize multiplication by constants!)
It is clear that, to the extent that "behavioral synthesis" is useful at
all, its proper domain is problems with substantial algorithmic content
and minimal temporal (state) content. These behavioral tools treat time
as an external "constraint" -- another dimension for optimization along
with power and gates. We think this sort of tool would find its best in
wireless application for BBPs (baseband processors). Our best-case
scenario might well be competing against multi-protocol wireless
interface products generated using behavioral synthesis tools!
- [ An Anon Engineer ]
Forte's Cynthesizer demo was good and showed the potential benefits of
the C to RTL methodology. The ease of design exploration possibilities
and tradeoffs impressed me. However, my impression was somewhat
peculiar as to the usability of these tools:
- They are intended for some specialized DSP designs only
- Their cost is sky rocketing
- It is a very big leap for hardware designers (who are generally
quite conservative)
- They ALL can now do excellent H.264 designs ...
My feeling is that something is missing there between the RTL and the C
layers because when looking on the verification field there are at
least 5 levels of abstraction between the two.
I was also impressed by the concept of the Synfora tool, though it is
a rather complicated solution. I also think CoWare LISA is a good
solution for some cases of DSP designs.
- [ An Anon Engineer ]
The purpose of my visiting Forte's DAC demo was to understand the
potential impact of Cynthesizer on our verification flow, speed
and quality. The tool had not yet been evaluated by our frontend
designers. My feedback from their DAC demo was that SystemC should
be very easy to integrate into our verification flow. Also, the
strong support of equivalency tools (eg : Calypto) may slow down
adoption, plus there might be partitioning issues regarding control
flow and data flow synthesis.
Now, months later, we have IP's developed using similar tools from
competition. We now have a better understanding on how and where
this class of tools can be efficient. For historical reasons
probably, we still haven't evaluated Forte. On the verification
side, we are not taking advantage of this new style of design; we
still base the verification at RTL level. The main reason is due
to the fact that only a subpart of the design is described in a
behavioral way, and verifying this part of our hierarchy "stand
alone" is not cost effective or meaningful.
- Laurent Ducousso of STmicroelectronics
Forte's DAC Cynthesizer demo was not detailed enough for me to talk
about its strengths and weaknesses. But I think the future of
behavioral synthesis is quite promising. The productivity gain of
SystemC will be degraded if the gap between SystemC and RTL is not
filled by a mature behavioral synthesis tool. Like logic synthesis,
behavioral synthesis will be successful once a full set of
synthesizable SystemC syntax is well defined.
- Joonhwan Yi of Samsung Electronics Co.
I think the Forte Cynthesizer demo was good and the tool promising. I'm
not sure how much behavioral synthesis is used today. It would be good
to see a real tape-out based completely on SystemC design and Forte's RTL
code generation.
I am a big believer of system design, but it has been one of those
elusive concepts that no one has capitalized on yet. Perhaps there have
been too many custom C++ system design tools (Agilent ADS Ptolemy, Elanix
SystemVUE, CoWare SPW, etc.) Customers have always been skeptical of
these and relied mostly on hand written RTL code. I see this development
similar to logic synthesis tools created for HDL back in 80s-90s.
- Shashi Bhutada of Agilent
Cynthesizer's biggest strength is that it supports SystemC, i.e. it can
be merged with other tools for a solid design flow. Its biggest weakness
is currently that it is limited to the module level.
- [ An Anon Engineer ]
Regarding Forte -- behavioral synthesis is really interesting, but we
don't plan to bring the tool in our flow for now. Breaking the boundary
of architecting, verification and implementation is my dream. I will
keep an eye on this tool.
- [ An Anon Engineer ]
Forte Cynthesizer certainly works, and evaluation results are good.
Hope to use it in the near future on suitable commercial projects
where its high price can be justified.
- [ An Anon Engineer ]
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