( ELSE 06 Item 4 ) --------------------------------------------- [ 06/23/06 ]
Subject: Denali Blueprint
FOR REGISTERS ONLY -- When I heard that Denali had created yet another HW
description language (this time just for the registers of a chip), I thought
it was a cheap ass attempt by an EDA vendor to snooker chip designers into
a proprietary language and it would fail. After all you can easily create
registers in Verilog/VHDL, "e", Vera, and System Verilog, right? Well, it
turns out some people are using RDL and Blueprint -- so who am I to kvetch?
I'd like to put my 2 cents in for Denali Blueprint. Some history first:
In the past, our ASIC teams dealt with coding, verifying, documenting
software assessable registers in several different ways. About 6 years
ago, we typically coded our registers by hand, coded the applicable
verification code ('e' in our case), and documented the registers all
separately -- which no matter how hard you try is prone to errors, let
alone a tremendous amount of duplicated effort.
A year or two later, we migrated to internal tools where we could
generate Verilog, 'e' and frame docs from a common text file. We
finally found a way to link RTL, verification and documentation
together through one common input file. Errors due to translation of
registers into the various formats were removed instantly. A lot of
time was also saved. The downside was the language was not overly
intuitive (people constantly going back to the docs to figure out which
switches they needed for a certain register type), not to mention we
were resource limited-and future advancement of the tool was simply not
going to happen. We're an ASIC shop, not a tools shop. At least that's
the story one gets from management.
Now in comes Denali with Blueprint. Where as our previous register
generator was a gigantic leap in advancement of time saved, migrating to
Blueprint has been a similar, if not more so of, a leap. Denali has a
tool that many language generators that are controlled from a common
RDL (Register Description Language) file. First off, RDL is a much more
intuitive language to describe register sets. In essence, it's an OO
like language where you can create bit or field objects, which can later
be instanced to create registers, and they in turn can be instanced to
create register files and address maps. Within each instance, you can
overload a particular bit, or register, or regfile properties. Simply
moving to an OO like language has helped tremendously to speed up the
development/description of our register sets.
One of the issues we've faced across the company is integrating various
IP from various groups. There ultimately will be a chunk of logic that
has been developed within another group, but all of the verification
effort was done in another language. Denali's Blueprint can generate
representative verification code in several languages-vera, e, SystemC,
System Verilog, and C. We can now immediately generate the supporting
code in a format that will integrate into our verification flow.
There's no more jumping through hoops in order to integrate something
like Vera into our 'e' flow. Another handy generator is an HTML
generator for documentation. Frame can be such a pain to scan through
thousands of pages of register descriptions. The generated HTML is
much easier to navigate, making verifying various blocks easier as
well as debugging the ASIC in the lab because you can get to the
information quicker. Lastly, we had always been missing a link to
developing code the software folks can use -- which is now remedied by
SystemC, C, C++, etc. output generators. We can now close the gap where
previously errors were introduced from when the software folks coded
the registers based on a sometimes suspect generated documentation.
Here's the kicker -- one of the most important parts of the tool; you
can easily create your own output generators! So in our case, some of
our eVCs needed our register 'e' code to be in a specific format.
Using the 'e' generator as a base, we were quickly able to create our
own customized output generator.
Lastly, there have been times where we've found the RDL language was
lacking. In order to overcome that, the language has the concept of
user defined attributes. Based on certain keywords that we've defined
internally, along with those really cool custom output generators I
previously talked about, we can now create very complex register
characteristics. We've also taken that another step where we've
created our own SW assessable objects (for example, think interrupt
register sets-status, various masks, interrupt counters, etc). These
objects can now be better linked into internally developed, higher
order eVC models. And best of all, we now have consistency within
all our modules within a given chip (due to several design members,
there was always at least one inconsistency within the chip, for
instance having a read to clear counter in one module, and a write
one to clear counter in another module).
Simply put, RDL, along with Denali Blueprint has not only increased
our productivity tremendously, it has also helped reduce design,
verification, and software errors while creating a much more
consistent end product.
- [ An Anon Engineer ]
First, it's quick. For the device registers that we have, Blueprint
runs in a matter of seconds. Second, it has a very nice backend
interface that allows a user to customize the output. The default
Blueprint product will produce various standard outputs such as C
header files, but the interface is documented such that we can add
custom output routines to generate anything that we need. Third,
the internal database is represented as Perl objects, and we use a LOT
of Perl in our design flows. Since the database is described, we can
do internal post-processing of the data as part of custom outputs to
add an analysis step. I assume that Denali and other Blueprint
customers use this same capability to create different tools out of
the back end of Blueprint -- a very nice feature.
- Michael Uhler of MIPS Technologies, Inc.
Recently we have been evaluating the 'Blueprint' tool from Denali. It
takes RDL (register description language) as input and outputs RTL,
verification environment and documentation for the associated
registers. Pretty useful.
- [ An Anon Engineer ]
Denali Blueprint
After an extended evaluation, we have now started using Blueprint. It
replaces our internal utility and flow addressing the same need, which
had limited capabilities. Even though the tool is based on a simple
concept, its impact on our development flow is big. Defining and
capturing the register space of our products in RDL by the central
architecture team and automatic generation of various related views
by RTL, verification, validation, software, documentation, partner and
customer engineers using Blueprint is tremendous value. We expect
significant reduction in related development, verification and
communication. The tool now has the basic capability. Denali support
team is very flexible and aggressive to address our advanced feature
and flow requirements.
- [ An Anon Engineer ]
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