( ELSE 06 Item 2 ) --------------------------------------------- [ 06/23/06 ]
Subject: Mathworks Matlab & Simulink, Elanix, Xilinx Accelchip, CoWare SPW
HONKINGLY COMPLEX ALGORITHMS -- Mathworks tools were orginally for nerdly
academics who wanted to calculate pi to 99 digits and they eventually
morphed into modeling messy DSP and imaging algorithms. AccelChip sold SW
that synthesized floating-point Matlab into fixed point VHDL or Verilog for
Xilinx & Altera FPGAs. There's been some questions about the future of
AccelChip now that it's been acquired by Xilinx. Synplicity also introduced
"Synplify DSP" which looks amazingly a lot like a AccelChip.
Matlab is used by some of the design teams. We had Elanix but no
longer use it.
- [ An Anon Engineer ]
Mentor's Seamless tool looks good so far.
Matlab is used in small quantities ~10. Elanix was used for about a
year then discarded.
- [ An Anon Engineer ]
Mathworks Matlab & Simulink: not practical for digital RTL design.
Maybe it's good analog designers?
SPW: is it still used somewhere?
Catalytic: announcements are impressive. Would need to check if it is
marketing or real!
Synplify DSP is similar to Mathworks Simulink-to-RTL flow; it lacks
time scheduling.
- [ An Anon Engineer ]
Accelchip sells a synthesis tool that takes a Matlab model, converts it
to fixed-point arithmetic and produces synthesizable VHDL or Verilog.
They can now export to Simulink and Xilinx. They have added the ability
to insert pipeline stages and unroll "for" loops.
Synplicity sells a tool called Synplify DSP that takes a Matlab/Simulink
description of your algorithm plus some user inputs from a GUI and
produces synthesizable RTL for FPGAs and a testbench. This tool also
can be targeted to an ASIC but you have to massage the result for RAM
instantiations.
- John Weiland of Intrinsix Corp.
Designs using tools starting from Matlab should be easier compared with
those tools starting from C, mainly due to the language issues. But the
MathWorks people are not hardware designers, nor EDA researchers. They
just wasted their advantages.
AccelChip is good but can't be called great.
- [ An Anon Engineer ]
AccelChip is very nice and easy to use. However, this tool makes sense
for a system level designer rather than a HW designer who typically
likes to have more control over the final hardware than Accelchip
allows. Excellent library of IP, good if you're putting a bunch of
blocks together. Very FPGA centric.
There are vendor specific tools for Simulink like Xilinx System
Generator. Allows for fine grain control over the HW but this is only
one level above schematic based HW design, not terribly productive.
- [ An Anon Engineer ]
Accelchip will be evaluated in the near future. There is now some
confusion because Xilinx owns Accelchip.
- [ An Anon Engineer ]
We compared MathWorks Matlab & Simulink + Xilinx SystemGenerator vs.
AccelChip and found that it was not worth it to spend so much money
for the AccelChip tool only to translate Matlab functions into more or
less usable RTL.
Better to spend less money in the Simulink/SystemGenerator flow to
design the datapath really quick and then take the time to hand code
the control logic. In the end we decided to go with Mentor Catapult
because it does the whole thing - datapath and control logic synthesis
plus verification. And we still can use Matlab analysis inside of our
C-code or externaly based on simulation result files.
- [ An Anon Engineer ]
We were evaluating AccelChip when they were bought by Xilinx. It does
OK if you write very straightforward (almost VHDL-like) Matlab. The
auto-quantizer doesn't work all that great -- so you have to go tweak
all the settings, and the complex library has lots of issues. It
looks like a tool that definitely has promise, but not quite ready for
me to completely trust-and also very buggy. I hope Xilinx chooses to
support AccelChip and develop it instead of just sticking it on a shelf
just so their competitors can't use it.
- [ An Anon Engineer ]
CoWare ConvergenSC is good but like all ESL tools is overpriced. We
would be using it right now if not for the price tag. It would be good
if ESL vendors realized that the boom in ESL will only happen when the
tools are value for money as there is a Cadence NC-SystemC that is
actually a lot better than expected and is good value for money if you
are looking for a SystemC simulator for architecture analysis and
RTL verification.
Matlab & Simulink rules here, particularly in the wireless area.
- [ An Anon Engineer ]
CoWare sells a suite of SystemC tools including what they claim is the
fastest SystemC simulator presently available. These tools have the
ability to mix transaction level SystemC models and VHDL or Verilog RTL
and support for ARM and MIPS. CoWare claims they can simulate an SOC
at 10-20 MIPS (last year it was 300-500 KIPS) enabling you to try out
your system software. They also have tools they got from LISATek,
which use their Language for Instruction Set Architectures (LISA) for
rapid generation of RTL code as well as compilers, assemblers, etc.
They also recently bought the SPW signal processing tools from Cadence.
- John Weiland of Intrinsix Corp.
We have Matlab and CoWare SPW and definitely use both for algorithm,
then FPGA development.
- [ An Anon Engineer ]
I'm not happy with these Matlab-based tools. Matlab is good for some
prototyping, but when it comes to creating a system it seems to be
lacking (and to be honest, I don't like the syntax). These Matlab-based
tools are aimed at DSP applications. It seems like some of the emerging
languages like Confluence are at least as good for this sort of thing.
You end up with part of your system designed in a very different way
from other parts of your system. I hope we (as an industry) don't go
too far down the Matlab road, and I feel like a better way of doing DSP
designs will emerge (though I have no idea what that is yet; I suppose
if I did, I'd start an EDA company. I understand why the Matlab tools
emerged, but hopefully they represent an evolutionary intermediate
solution.
- [ An Anon Engineer ]
Matlab and Simulink are more popular.
- [ An Anon Engineer ]
No SystemC/C tools here. Most algorithm/model development is done in
Matlab. We've linked the Matlab C interface into a System Verilog
testbench (using the DPI) but the interface is clunky and not usable
for Matlab designs of significant complexity. Dumping data to files
from Matlab sims and sucking it into Verilog testbenchs is the main
mechanism used to verify models vs. RTL. Would be easier to compare
RTL vs. model if algorithm developers used SystemC. It's got better
integration with RTL simulators. But SystemC's coding overhead and
learning curve coupled with Matlab's ease-of-use make sure SystemC
remains left on the bench.
- [ An Anon Engineer ]
SystemC and Matlab are nice ideas, but having tried to use them, we've
gone back to ISS for SW guys and RTL for HW guys and linking them
together at the emulation stage. This whole area seems way too
immature right now.
- [ An Anon Engineer ]
Having a reference in Matlab or C/C++ and re-writing this in VHDL or
Verilog RTL is tedious and error prone and probably not the best job
for a creative engineer.
- [ An Anon Engineer ]
Matlab -- powerful tool that helps me all the time evaluating new ideas.
- [ An Anon Engineer ]
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