( DVcon 07 Item 13 ) -------------------------------------------- [ 05/24/07 ]
Subject: IEEE PSL, System Verilog SVA, Verplex OVL/IAL, 0-In CheckerWare
LOTS OF NEWBIES -- The two big trends I found were SVA assertions now lead
the pack and there are now lots of beginner assertion users.
2005 - What do you think of assertion languages and assertion
libraries such as SVA, PSL, OVL, 0-In CheckerWare?
don't use : ########################################## 42%
IBM Sugar/PSL : ##################### 21%
0-In CheckerWare : ######## 8%
System Verilog SVA : ################## 18%
Synopsys Vera OVA : ############ 12%
Verplex OVL : ############## 14%
VHDL Assertions : ## 2%
2007 - Does your current project use assertion languages or assertion
libraries? (Yes/No) If yes, which one(s) are you using? (e.g.
IBM Sugar/IEEE PSL, System Verilog SVA, Verplex/Accelera OVL,
Synopsys Vera OVA, 0-In CheckerWare, VHDL assertions, homegrown?)
don't use : ################################ 31.5%
IBM Sugar/PSL : ############### 14.9%
0-In CheckerWare : ####### 6.8%
System Verilog SVA : ###################################### 37.8%
Synopsys Vera OVA : ########## 9.6%
Verplex OVL/IAL : ######### 9.3%
VHDL Assertions : ####### 7.0%
homegrown : ######## 8.2%
Be warned: I think the VHDL and the homegrown use did NOT go up, it's just
that the 2005 question didn't suggest either of them as an option while the
2007 one did. (Read the text of 2005 question closely above.) My bad.
The stats clearly show assertion use (in general) has gone up (in 2005 42%
said "don't use" which has dropped in 2007 to 31.5% who said "don't use")
and that assertion use has switched waaaaaaaay over to System Verilog SVA.
In fact, if you look closely, you'll see that the PSL, 0-in, OVA, and OVL
assertions all *decreased* by 1/4 to 1/2 in use from 2005 to 2007; while
SVA use has jumped by 2X (i.e. it went from a middle-of-the-road 18% to
grow to a definite leading-the-pack 37.8%).
As a sanity check, I called Gary Smith about this. He said: "That explosion
of SVA use makes perfect sense to me. Yet again, I'm seeing the exact same
data. It's the SVA assertions that's been the driving force behind System
Verilog acceptance. Without them, I doubt SV would have grown as quickly as
it has. System Verilog is taking over, just as we all expected."
Now, only counting those who actually use assertions, I asked:
2007 - In your project are assertions used by designers, verification
engineers, or both? Are assertions "useful" or "busy work"?
designers : ########## 19.2%
verification : ############ 24.6%
both : ############################ 56.2%
useful : ############################################# 89.4%
busy work : ##### 10.6%
2007 - In your experience, do assertions work the same in all tools?
yes : ####### 14.5%
no : ######## 16.1%
don't know : ################################### 69.5%
What this points to is a whole lot of assertion first timers! The bulk of
the users (~70%) couldn't tell whether assertions worked the same in other
tools because they were predominantly using assertions in only one tool.
In other words: newbies!
3.) Does your current project use assertion languages or assertion
libraries? (Yes/No) If yes, which one(s) are you using? (e.g.
IBM Sugar/IEEE PSL, System Verilog SVA, Verplex/Accelera OVL,
Synopsys Vera OVA, 0-In CheckerWare, VHDL assertions, homegrown?)
In your project are assertions used by designers, verification
engineers, or both? Are assertions "useful" or "busy work"?
In your experience, do assertions work the same in all tools?
(Yes/No) Which tools remain true to the assertion standard?
Just beginning to use assertions. SVA and VHDL assertions.
Mostly verification guys using them now. Minority think they're
useful, oldtimers resistant.
Don't know.
Yes, we use Synopsys Vera OVA.
Mostly verification engineers are implementing assertions, but some
are being added by designers, and we plan on more from design.
I'm not sure, this is kind of new to us.
System Verilog SVA (Synopsys VCS built-in) plus homegrown.
Both. Depends on who you ask. We see value but are struggling with
wide spread adoption due to schedule pressures.
Don't know. Only have experience with Synopsys, works pretty well.
Should be able to answer this question a lot better next year.
System Verilog SVA
Designers. Busy Work
No, so far a lot of work, not much success, only tried on VCS.
No assertions, but plan SVA
System Verilog
Both, and useful.
Yes (since we only use them in one tool , ie.e VCS...)
No, but some designers use VHDL assertions on their own
useful for skilled designers, for the others busy work.
We use some of the System Verilog checker library stuff that ships
with VCS, we do both design and verification ourselves here so I
guess both, they appear to be quite useful but not the panacea
Synopsys make them out to be without using them with formal (that
we currently don't do!). In the future we'll be feeding back our
STA constraints and exceptions back into the verification via
assertions, it'd be cool if someone could automate this.
Yes. We are using assertions - System Verilog SVA.
verification engineers mainly for protocol checking. Useful.
don't know
Yes, IEEE PSL
Designers, useful
Don't know
Use OVL.
Both. Useful for debug.
Don't know.
Limited SVA assertions
Useful
Not 100%. Synopsys seem to be tighter to the standard than Cadence.
PSL in an minimal, ad-hoc way
useful, but we do not use them enough
No idea. Using only Cadence simulators
No.
Maybe useful. But no time to do assertions.
OVL
We use both (depending on the block). They are useful.
No comment, need to check with other people.
System Verilog SVA
both
No, Questa best. Synopsys Vera OVA worst.
System Verilog SVA and homegrown.
Both, useful.
Don't know
Yes - System Verilog SVA
Too early to tell - first project with assertions.
Don't know
VHDL-Assertions, PSL, ITL (OneSpin Solutions)
We do not seperate design/verification engineers, so both use.
no answer
Yes - 0-In CheckerWare
Inserted by designers - they are useful
Yes
PSL, Modelsim QVL (CheckerWare), homegrown VHDL assertions
Too soon to tell - currently working on first project to use them
Don't know
No. (Actually, one engineer has used it a little, but it is by no
means widespread and is not officially part of our flow.)
The one engineer wears both hats. In my opinion, they are very
useful. My homegrown assertions have popped up several times and
pinpointed problems that would have been mysteries otherwise.
I don't know.
We use a mix of SVA (now preferred) and OVA (legacy).
Used by both. Assertions are an essential part of our validation.
No, subtle differences exist. No tool is noticibly more or less
faithful to the standards than others.
Homegrown.
Designers; useful/critical to preventing bugs from creeping in.
Don't know.
No.
Both (past project) - currently viewed as "busy work" by some,
"useful" by others. Their utility is very chip dependent.
PSL
Designers / useful
Don't know. We only used assertions in NC-Sim and IFV.
System Verilog SVA
Both. Useful, but take some learning to get the most benefit out of.
Haven't experienced that.
PSL
actually by verifiers, very useful -- but shift to designer (to
catch his intend) is necessary.
Yes, work same.
SVA
Useful - used by both Designers and Verification Engr.
Yes - Mentor does
Yes, PSL assertions.
Both designers and verification engineers.
Don't know. PSL only used in Cadence IUS tools (NCSim and IFV).
System Verilog SVA
Designers (no verification; the designers do it all). Useful.
No experience with different tools. Don't know.
Yes: SVA and Temporal 'e'
Used by both... minimal use by design... different use by verification.
Questa is totally true and fully featured for SVA. Closely followed
by Synopsys. Most SVA assertions work reliably across both these
tools. Cadence still lags by some way and does not yet support the
full feature set.
Temporal 'e' expressions may be true to the language, but the language
is not true to real-world time! The scheduling semantics of SVA are
just not there for temporal 'e' often resulting in race effects and
unreliably effects when using Specman bound to different simulation
kernels.
Yes. System Verilog SVA.
Both. Useful but definitely more work up front.
?
Yes, System Verilog SVA
Both, useful.
Yes, however we only use Synopsys tools.
VHDL assertions. Have used PSL, SVA and OVL in the past.
Both. Useful.
Don't know.
Yes. PSL.
Verification Eng. Useful.
No. Cadence and Mentor simulators had different results. I'm not
sure which one is right, it was mainly a "coding style" problem.
System Verilog SVA used by verification engineers for testbench
development. Goal is to be non-vendor proprietary however Synopsys,
but not Cadence currently support the assertions we want to use.
Don't know.
PSL
Both -- I think they are useful
Don't know. Only used in Cadence
0-in CheckerWare.
Both designers and verification. Assertions have been very useful
to us. Mainly for speed of debug when one trips. (i.e. FIFO
overflow). Occasionally an assertion finds a bug that does not
propogate to the outputs.
Don't know. I guess 0-in is proprietary. It works well though.
PSL.
Assertions used by designers. Quite useful.
I don't know.
We use VHDL assertions and are starting to use PSL
Assertions are primarily used by the designer. They have been useful
for regression testing when new "features" have been added.
Unknown. We've only use assertions with the Mentor tool set.
Yes. We use PSL, OVL and some homegrown ad hoc stuff.
Both. I'm not sure how effective they are.
Not sure.
We do not use any assertion languages.
SYSTEM VERILOG SVA
VERIFICATION ENGINEERS. BUSYWORK -- NOT ENOUGH PEOPLE KNOW HOW
TO USE THE TOOL EFFECTIVELY.
DUNNO -- ONLY EXPERIENCE IS WITH MENTOR SVA, WHICH I HATE.
Yes: mostly PSL, some SVA. SNPS and CDN deliver OVL-like libraries
in PSL that we use.
Both. Useful, sometimes very useful.
Minor variations get ironed out over time. NC is very slightly more
accurate than VCS for PSL, but that difference is almost gone. VCS
and NC-SIM both have tool-specific PSL 'severity' constructs.
PSL
- verification mainly, "top level" assertions to check temporal
expected behaviour. not easy to modelise in C/SystemC PV model.
fast deployment 10's to 100 assertion per IP's.
- designer, few microarchitecture level assertions, for static check
IFV/CDN or simulation. very slow deployment.
Don't know. only IUS/Cadence and IFV/Cadence use.
0-In CheckerWare.
Both. Somewhere between useful and busy work. We've caught some
important bugs with them that most likely would have slipped through,
but they are a pain in the butt, sometimes spending more time
debugging assertions than the design.
Yes.
Yes PSL, OVL, VHDL assertions.
both (depends on designer and verifier) and useful.
I've never noticed a difference but we don't use a variety of tools.
Current project does not use assertions.
Starting SVA.
To be used by designers. Better not be busy work!
Do not know.
Yes. IEEE PSL.
Used by designers and verification engineer. Considered as useful.
Yes. Cadence NC as far as we have used it.
Currently No, planning on Yes; System Verilog SVA
Currently none, will be both; useful
Do not know.
Yes. We use OVAs and are transitioning to SVAs (in VCS).
Both. They are useful.
Don't know. I am familiar only with VCS.
No extensive usage of assertions yet, spot usage of SV SVA
Mostly designers. Assertions could be useful if written effectively.
Can't comment, use only VCS for sims
Current project is just starting out. Plan is to use Accelera OVL
(Verilog versions) rather than SVA as Spyglass currently does
not support SVA.
We identified a few places where it will be useful but truthfully
I don't think we know whether it is useful or busy work. To me it
seems like a lot of promises are being made about their effectiveness
but there seems to be no clarity in how useful they are.
Not applicable as we are just starting to use them.
System Verilog Assertions, Open Vera Assertions
Both. Very useful.
90% of the time. There are some issues across tools in regards to
support hierarchical bindings, concatenation and sliced bit vectors
used in bind module block.
We do not use assertions. Mostly because it's "busy work".
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