( DVcon 07 Item 12 ) -------------------------------------------- [ 05/24/07 ]
Subject: System Verilog
GROWTH, BUT NOT FOR DESIGN -- While the data shows System Verilog use has
gone up 2X in the past 2 years, precious few engineers are using SV for
actual chip design. The bulk are simulation and verification users.
2005 - Do you see your project using System Verilog in the next 6 months?
yes : ########## 19%
no : ######################################## 81%
2007 - Excluding assertions, is your project using System Verilog? (Y/N)
yes : ################## 35.1%
no : ################################ 64.9%
I asked Gary Smith about this and he said: "Interesting. My data shows 36%
for System Verilog use and they are almost all for verification, not design
use. Our data is dead on with each other. It's interesting that you broke
out assertions here. I didn't do that cause I assumed if you're using SV
and if you had a brain in your head, you'd be using its assertions, too."
Asking only those people who are using System Verilog:
2005 - Do you plan on using the System Verilog
design or the verification extentions, or both?
verification : ################################### 70%
design : ## 5%
both : ############# 26%
2007 - Are you using System Verilog for testbench
or design or both?
testbench : ######################################## 80.2%
design : ## 4.1%
both : ######## 15.8%
It seems that System Verilog (like SystemC) is still stuck in the role of
being mostly a verification language. I followed up with:
2007 - Have you taped out a chip using System Verilog for design, for
verification, for both, or "no-tape-out-with-SV-yet"? (Choose)
design tapeout : # 1.8%
verification tapeout : ######## 16.1%
both tapeout : # 1.3%
no tapeout yet : ######################################## 80.8%
Tapeouts involving SV is as rare as hen's teeth! What the hell is going on
here? It's not like Synopsys R&D has just now seen the SV language for the
first time! What's holding back Synopsys on SV synthesis?
Again, asking only the actual SV users in 2005 and 2007:
2005 - Whose System Verilog tools are you using?
Synopsys VCS : ####################################### 79%
Mentor ModelSim : ######## 15%
Cadence : ### 6%
2007 - Whose specific System Verilog tool(s) are you using?
(Include everything from simulators to synthesis.)
Synopsys DC : ##### 10.6%
Synopsys VCS : ################################# 65.6%
Synopsys Leda : # 1.8%
Synopsys Formality : # 2.6%
Synopsys VMM : ### 6.2%
Synopsys Magellan : 0.4%
Mentor ModelSim : ###### 12.3%
Mentor Questa : ######## 15.0%
Mentor AVM : # 0.9%
Cadence NC-Sim : ############ 24.7%
Cadence RTL Compiler : # 0.9%
Atrenta Spyglass : # 1.8%
Novas Verdi : # 2.2%
all others : # 1.3%
Looking at the VCS numbers, if you're not awake, you can come to the wrong
conclusion that it's use for SV was going *down* (79% going down to 65.6%).
But remember in 2005, 19% of all projects were using SV -- meaning that 79%
of 19% = 15% of all projects in 2005 used VCS for SV. In 2007, 35.1% of
all projects used SV -- meaning 65.6% of 35.1% = 23% of all projects used
VCS for SV -- which is a net gain; 2007 23% over 2005 15% of VCS for SV.
The stats start the story. While SV use has grown 2X over the past 2 years,
it still isn't the norm (only 35.1% use it). Synopsys owns the lion's share
of the tools in the SV market -- a market which is mostly simulators, not
synthesis tools. And from the user comments, you'll find your typical SV
user is a newbie still trying to get his first SV tapeout completed -- plus
he's not too happy about the crappy SV support his tools get.
5.) Excluding assertions, is your project using System Verilog? (Y/N)
If yes, are you using System Verilog for testbench or design or
both? (Choose) Whose specific System Verilog tool(s) are you
using? (Include everything from simulators to synthesis.)
Have you taped out a chip using System Verilog for design, for
verification, for both, or "no-tape-out-with-SV-yet"? (Choose)
Yes. Testbench. It's the wild west out there in System Verilog land.
We like Mentor/Questa, and are encouraging Synopsys and Cadence to
improve. Nobody matches anybody else, so delivering standard code is
quite a challenge today. Kind of like Verilog before we had the
industry wide acceptance of synthesizable subset. No tapeout yet.
Tried to use SV for design. Tool chain support is non-existant for
what we wanted to do (interfaces), so fell back to arrays of wires.
no-tape-out-with-SV-yet
No. We started to switch to it for design a while back but discovered
that the tool chain was not yet mature enough.
We had a couple of people try using SV for their design. Great
language, but the tool support was not there. We had problems
getting DC, LEDA, VCS, Formality, and Synplify Pro (FPGA-based
prototyping) to all agree on what to support. We finally gave
up and went back to V2k (or V95). We use a little bit of SV
features for test benches still. No tapeout yet.
Yes, for testbench. Synopsys: VCS-MX, VMM, no-tape-out-with-SV-yet
Yes, both for testbenches and design. VCS, Leda, Formality & DC.
Tapeout not yet, but should happen any day now.
We use very basic System Verilog constructs in our test-benches. We
wanted to use interfaces throughout our design, but found that it
wasn't supported all the way through the Synopsys flow and made our
intentions moot! no-tape-out-with-SV-yet
No System Verilog other than assertions.
Yes. We have used System Verilog for testbench. (simulator - VCS)
We have not used System Verilog for design.
YES for testbench and some RTL. VCS and Altera Quartus II.
no-tape-out-with-SV-yet
HA HAHAHAHAHAHAHAHAHAHAHA
That would imply that System Verilog is even supported by our Cadence
tool chain. Try asking Cadence if you can use the SV31 flag with
UltraSim/AMS (in their defense, it might be by now). Even if it was,
SV for testbench is a committee-designed mess. SV for design is nice,
and SVA is fine, but see previous toolchain comment. You ask about a
tapeout? HAAAAAAAAAAAAAAHAHAHAHAHA *um* I mean: no-tape-out-yet
Yes. System Verilog for testbench only. Design is Verilog 2001.
Synopsys VCS. no-tape-out-with-SV-yet
Yes. Testbench only. Synopsys VCS. no-tape-out-with-SV-yet
Yes, TB-only; Mentor Modelsim - but only the free bits - not Questa.
Yes tapeout for verif - same as above - only the free bits.
Y, Both, Questa SV. no-tape-out-with-SV-yet
Yes. Using for testbench. Modelsim and VCS.
Tapeout within next 2 months using SV for verification.
Yes. Testbench. Mentor QuestaSim. Yes tapeout for verification.
No. Have used SV in the past for verification.
Verification tapeout on previous projects.
Using System Verilog for more than assertions in creating testbenches
(not design), using VCS (not synthesizable). Just starting with
Synopsys Magellan. No-tape-out-with-SV-yet.
Yes -- testbench only. Cadence IUS 5.83. Not used in chip design.
Starting to play with System Verilog for testbench using both VCS and
QuestaSim. Both have issues but I can actually compile and run our
code with Questasim that VCS barfs on. no-tape-out-with-SV-yet
No, we do to see them in contractor designs in the next year or so...
Yes, SV constraints are used in our testbench code. Cadence's NC-Sim
is used. no-tape-out-with-SV-yet
No. Next project will use System Verilog for testbench. Tools not
yet defined.
SV for testbench, not design. Designers are encumbered with crappy
Virage tools that don't even support verilog 2001 (RAMs inside a
generate statement), so they're afraid to do anything with SV keywords.
no-tape-out-with-SV-yet
Yes. For testbench only. Cadence NC-Verilog only. no-tape-out
Yes, testbench. Mentor Modelsim. no-tape-out-with-SV-yet
No use of System Verilog
No System Verilog, Verilog only in Modelsim
Yes, only for testbenches to run on VCS and ModelSim. no tapeout.
Mostly testbench, a few cases embedded in design RTL. Cadence simulator.
no-tape-out-with-SV-yet
No on System Verilog. We will not move to SV until it is supported
thoroughly by all 3 simulators. We will watch the Cliff Cummings
reports to measure that.
We have not yet used System Verilog. We will likely incorporate it
into the next project mostly for design. We are unsure that SV could
support writing the very complex checker components that we write in
our verification environment.
Excluding SVA, we use System Verilog for verification only. We are
about to tape out the chip we used it on. We use Cadence IUS 5.6.
Limited, but useful System Verilog support. The primary hinderance
to use in RTL design is the lack of SV support by tools further down
the chain such as LogicVision BIST tools. no-tape-out-with-SV-yet
We used System Verilog for testbench from Jan-06 to Jan-07. We were
using Mentor Questa/ModelSim, and were pleased. We have now moved
onto another project, using VERA and Synopsys VCS. We are modifying
an existing VERA environment. This is not a from-scratch testbench,
otherwise, we're probably use System Verilog again. We were 1 month
away from an ASIC tapeout, having used System Verilog for testbench
only. Our project was put on hold, and we've shifted to another ASIC
whose testbench uses VERA. So technically, "no-tapeout-with-SV-yet".
Yes, testbench. Mentor QuestaSim. Tapeout for verification
Yes. Testbench only. Primarily MC-Verilog (40 copies) and 2 VCS.
Verification only has taped out about 6 chips.
Yes - both. But mainly using System Verilog for testbench and
verification. We are using Cadence simulator - but they are "WAY
BEHIND THE CURVE" on supporting many of the features of SysV. This
is major reason we are evaluating Mentor. "no-tape-out-with-SV-yet"
Yes. Testbench. Cadence NC-Sim for simulators. Have no synthesis
support. no-tape-out-with-SV-yet
I've begun to use SV for test-bench design, I would also like to use it
for design as it has a lot of great features that enhance productivity.
I'm using Mentor for simulation and Synopsys for Synthesis. But again,
If the language is standardized, then the tool is just a matter of
preference. no-tape-out-with-SV-yet
No, but we are trying System Verilog in a "sandbox'.
Currently, SV for testbench but plan to use it for design. We use
NC-Verilog. Looking at switching to VCS because their simulator
offers more support for System Verilog. no-tape-out-with-SV-yet
Are you kidding me? We still can not get consistent implementation
on Verilog 2001.
We're using SV in VCS for all unit-level testbench development, the
verification team loves it. Other than assertions, most designers
have been uninterested in SV constructs. (Old dogs... new tricks...)
Yes, tapeout for chip containing units which have been verified in
unit-level SV testbenches. Not for entire system-level SV testbench.
We have just started a project using System Verilog for testbench.
The project is starting with Synopsys VCS and VMM library. Unless
you count SVA, no tapeout.
No. We have kept current on SV, but our investment in our own C++
classes makes it difficult to change verification environments.
Yes, testbench. MTI and NC No SV in design. Only testbench.
Yes. Mostly for testbench, the only feature we use for design is
SV "interface". Synopsys VCS and design compiler. No tapeout.
In one consulting project last year we started implementing protocols
in SV using BlueSpec and ModelSim. Describing the protocols FSM
behavior in SV was neat, and the first outcome was very promising but
the client decided to put the project on halt. (not Bluespec's or
SV's fault). No tapeout, but probably we would have.
Not yet but we will be using SV for verification within 2 years.
Our group has not previously used System Verilog. Our new project
will, primarily for testbench. NC-Verilog, possibly VCS-NTB.
Yes for testbench. AXIOM design automation. no-tape-out
We're a VHDL house. No-one is using System Verilog AFAIK.
Yes. Testbench. Cadence NC Verilog, ModelSim SE & Questa.
no-tape-out-with-SV-yet
Yes, but really we are only using 1 small feature of System Verilog
for our testbench (packed arrays). VCS. We certainly aren't doing
VMM style testbenches. Although we are looking to do that in the
future. Our RTL is straight Verilog 95/2001. Synopsys DC.
Yes, just verification. Mentor QuestSim. "no-tape-out-with-SV-yet"
but getting close.
Yes. Only in the testbench. VCS simulation. We have not had to
try out any of our other tools against the SV syntax since it does
not spread out to the design, and we `ifdef around any SV syntax
for the benefit of our debugger (Verdi). Verification tapeout.
No: 95% of our customers (Europe) are VHDLers.
The 5% Verilog is not geared up (yet) in SV !
But we are eager to see this change : we will love using SV.
Yes, we will use SV testbench in current project. Primarily Mentor
Modelsim/Questasim, plus a few seats of Cadence NC-Sim. We are not
using System Verilog for design, because there are too many tool
inconsistencies throughout the flow (simulation + synthesis +
equivalence check). "no-tape-out-with-SV-yet"
Yes. Testbench. Cadence NC-Sim. Yes, verification tapeout only.
Using System Verilog for both testbench and design. Were earlier using
Questa. Did some work on evaluation of it. Now using Synopsys and
ModelSim tool for SV. "No-tape-out-with-SV-yet"
Yes. Mainly testbench. Design coding is limited by lack of SV
support in Xilinx tools. Mentor Questa.
Not yet but the TB will be in SV in the future.
Yes, for design and testbenches. Synopsys VCS and DC. Yes, one
tapeout using System Verilog for design.
Yes, we use System Verilog (+ VMM from Synopsys) for verification.
Synopsys VCS. Taped out a part which used a SV testbench verifying
a part of the chip.
No. However, we are seriously looking at it for both verification
and design.
Yes, for both. Synopsys VCS, Synopsys Magellan, Synopsys Formality.
My project is an IP Core for the Interlaken protocol. Some customers
are still using a Verilog95 CAD flow, so we have an internally
developed Perl script to convert the System Verilog (and Verilog-2001)
constructs into legal Verilog95. Synthesis then runs through any tool
the customer wants. We use Synopsys Design Compiler. no-tape-out
No, we plan to adopt System Verilog for verification this year.
Not now. We're moving to System Verilog testbenches & infrastructure,
using QuestaSim. Design will still be pure Verilog.
Yes for the testbench. VCS hands down supports 10X more than Cadence
so that's what we use. We are hoping Verdi can support more and more
SV constructs. no-tape-out-with-SV-yet
No System Verilog
YES, for testbench only. Mentor QuestaSim. We do not synthesize SV.
no-tape-out-with-SV-yet
Not yet
We are just starting to use System Verilog for building dynamic
random test generators (testbench only). Cadence NC-Verilog. On the
design side adoption is much slower. We do not have a tapeout with
System Verilog yet but I hope to have a couple next year.
No, our project does not use System Verilog.
Yes. We use for testbench. We use Mentor Questa with AVM library.
no-tape-out-with-SV-yet
Not yet, but will be shortly. Will be a shared Specman e talking
to SysVerilog testbench.
Yes. Only testbench. Mostly VCS. Modelsim's support for System
Verilog constructs is flaky at best. No-tape-out-with-SV-yet
No. The goal is to move the SV in the future (not yet defined).
No. Benchmarking only.
No SV used for design and very limited usage of SV-TB (mostly
evaluation purpose)
Yes, testbench, VMM. No tapeout.
Yes, we use SV for the testbench. Synopsys VCS 2006.6. There may
be a few minor uses of SV in the RTL. I think just the syntax of
specifying input/output in the module IO list (enough to need
the -sverilog switch for VCS compile). Count us as yes, if you
count FPGAs as tape-out. Our design target is the FPGA, not an
ASIC, and it's running in the lab.
We use only SV for testbench with VMM of Synopsys. Sim is VCS.
"no-tape-out-with-SV-yet"
Using System Verilog functional coverage; not currently used for
testbench constructs such as generators/checkers or for design.
The SV functional coverage constructs seem to be more mature under
VCS; Cadence NC support is lagging. No tape-out with SV yet.
Not yet, planning on using it this project; testbench; Synopsys
We are beginning to use SV for verification. I don't think designers
are adopting it in a significant way. We use VCS exclusively at the
moment. no-tape-out-with-SV-yet
No. There are tentative plans to use some SV for verification and
probably SV on next project for design.
Yes, we use System Vevilog for modeling, and testbench. We use
Synopsys so far, plan to also use Cadence tool when they catch up.
Tapeout for verification only.
No real SV usage yet.
Some SystemVerilog constructs in the testbenches and some syntax
added the designs, but nothing major. NC-Verilog. No tapeout.
SV used for verification, and to interface with C. VCS. In a
nutshell, following VMM. no-tape-out-with-SV-yet
No. But, I have been looking at System Verilog for developing
testbenches in my future projects.
No. SV used for assertions only.
We are transitioning from using Verilog for design and Vera for
verification to System Verilog (Synopsys VCS) for both, no chips
taped out yet.
Yes, testbench, NC and VCS. No-tape-out-with-SV-yet
No use of SV yet.
No SV on this project. Previously used VERA RVM with VCS-NTB.
No, haven't used System Verilog yet. May use it in the future to
replace Synopsys VERA/Native Testbench.
Yes. Using System Verilog for testbench. Synopsys VMM and VCS.
No-tape-out-with-SV-yet.
No System Verilog on this project.
Yes, I use System Verilog for testbench. Questa, VCS, NC are using.
Verification tapeout.
Yes. We are working only with FPGAs. No ASIC projects. We have
developed one design which has been described fully in SV in Mentor
QuestaSim. That was for Altera FPGA. Synthesis was Quartus II 6.1.
No. Experimenting with SV testbench usage.
Not at the moment, but could be used for verification. Tools and
language are not determined, but the tools supporting System Verilog is
not investigated, yet.
Not yet - we're headed that way.
Excluding assertions? No. No tapeout yet, except some where SVA
was used.
Nope. So far, we're using System Verilog only for assertions.
Yes. Testbench. Cadence Incisive.
Not for design yet except in some IP that we use.
No, just assertions. Vera for testbench. Plain Verilog for design.
No. We use VCS native test bench (NTB), which is supposed to be
similar, but I'll call it different. no-tape-out-with-SV-yet.
No System Verilog. Why do we need it? We use a superior language,
VHDL, for all our design and verification.
Yes, not just for assertions. Were using Verilog 2001 constructs in
RTL, but the "real" System Verilog stuff (Synopsys' VMM stuff, classes,
semaphores, smart queues, etc.) in the testbench. no-tape-out-yet,
but unless the project gets cancelled we will.
No. Might consider in the future when all tools support it.
Yes. For design only. Cadence NC-Sim, Synopsys VCS, Synopsys DC.
No-tape-out-with-SV-yet
No, not on current project. Next project would be Vera again or
Synopsys System Verilog. But not for design part.
No, plan to use in future.
No, but we'd like to. SV tool support for design and testbench
wasn't far enough along when we started this project.
YES, for testbench and design. SV tools are ModelSim/Questa and
Synplify Pro/Premier. FPGAs only, can't afford ASIC NREs any more.
Don't use System Verilog now, but will be in the future.
Not Yet. Plan to use Synopsys.
No. We will be migrating to SV from VERA for next project.
No. We constantly evaluate SV and believe that we will eventually
migrate to SV but continue to have too much leveraged code (design
and verif) to make a complete cut over to System Verilog. We've
also encountered issues with "just running SVA's" assertions with
v2k code in our evaluations, so we have not found a way to
incrementally migrate over. I see System Verilog as an all or
nothing (including design and verif). We don't want to get into
a binary compatibility evaluation, which we've had some discussions
with Synopsys about.
Yes. System Verilog for testbench. Useful design constructs not yet
supported by Synplicity's FPGA tools. Cadence NC-Verilog, Synopsys
VCS, Design Compiler. no-tape-out-with-SV-yet
Yes. System Verilog for testbench. Cadence IUS.
no-tape-out-with-SV-yet (it is going to happen in 2 weeks)
Yes. VCS, DC, Spyglass, Synplify, NC-Sim. However, the tool support
for System Verilog is still very patchy.
Synopsys seem to at least *understand* (i.e. parse) everything, have
done most of the useful bits (I think everything we really wanted
design wise), but will occasionally (politely) inform you that it
doesn't support a particular feature (mostly obscure testbench stuff).
Due to limitations from tools in the rest of the flow, the subset of
SV in use is a lot smaller than we'd like.
Synplicity is the main culprit - they seemed to have ignored all the
useful, easy bits (like enumerated types, just like they *already*
support for VHDL) and put in a couple of features no one would ever
use (in our humble opinion). They also still don't understand
reg/logic. Declaring what would have been wires as logic can silently
fail in strange ways - latches inferred, or similarly *wrong* logic,
that only gets found in an exhaustive check of the schematic viewer
or a sim of the output. no-tape-out-yet (Give us another 6 weeks.)
Yes. TB only. Cadence but moving to Synopsys. Taped out TB only.
No. We are looking at making the next project a SV testbench. We
think we will be using VMM.
Not at present. Planning to use SV for testbench later.
No. Future project will use SV for TB.
No. But we are steadily weighing the use of SV for testbench as it
takes less time to run. Initial bench marks show time reduction of
20-40%. We are further validating that.
Not using SV as an active language; still evaluating whether it's
appropriate for us (immature in most simulators & missing features).
We are not using System Verilog yet but it is planned.
No. But is looking at migrating whole testbench to.
Yes, for both testbench and design. We use Cadence and Synopsys
simulators and Cadence synthesis. We have taped out using SV for
the testbench and are about to tapeout with SV in the design.
No. This year we have planned to deploy it.
Excluding assertions, we don't use System Verilog.
No. Mostly assertions right now, there are still too many tool
gaps in support of SV to completely move over. Phase 2 is design
constructs for which we have been slowly starting to use some.
Testbenches won't be for a while.
Yes. Design. Verdi, SimVision, DC, RC, Spyglass, Conformal,
Incisive Code Coverage, Incisive Formal Verifier, 0-in CDC,
SpecMan, Incisive Unified Simulator, Spyglass, HAL.
no-tape-out-with-SV-yet
No, but I'd like to start using SV/SVA for verification. Don't know
if it's mature enough for design. I'm worried about inconsistencies
among the tools, particularly between the ASIC and FPGA tools.
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